IDT
®
Two Output Differential Buffer for PCIe Gen1 & Gen2 852 REV Q 08/27/13
ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
8
General SMBus serial interface information for the ICS9DB102
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D4
(h)
• IDT clock will
acknowledge
• Controller (host) sends the begining byte location = N
• IDT clock will
acknowledge
• Controller (host) sends the data byte count = X
• IDT clock will
acknowledge
• Controller (host) starts sending
Byte N through
Byte N + X -1
• IDT clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D4
(h)
• IDT clock will
acknowledge
• Controller (host) sends the begining byte
location = N
• IDT clock will
acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D5
(h)
• IDT clock will
acknowledge
• IDT clock will send the data byte count = X
• IDT clock sends
Byte N + X -1
• IDT clock sends
Byte 0 through byte X (if X
(h)
was written to byte 8)
.
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
IDT (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
PstoP bit
X Byte
Index Block Write Operation
Slave Address D4
(h)
Beginning Byte = N
WRite
starT bit
Controller (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T starT bit
WR WRite
RT Repeat starT
RD ReaD
Beginning Byte N
Byte N + X - 1
N Not acknowledge
PstoP bit
Slave Address D5
(h)
Index Block Read Operation
Slave Address D4
(h)
Beginning Byte = N
ACK
ACK
Data Byte Count = X
ACK
IDT (Slave/Receiver)
Controller (Host)
X Byte
ACK
ACK
