Signals Balls
E3
E4
E5
EPCQ-L Device Pin Description
Table 8. EPCQ-L Device Pin Description
Pin Name Pin Type Description
nCS
Input
The active low nCS input signal toggles at the beginning and end of a valid operation. When
this signal is high, the device is deselected and the DATA pin is tri-stated.
When this signal is low, the device is enabled and is in active mode. After power up, the
EPCQ-L device requires a falling edge on the nCS signal before you begin any operation.
DCLK
Input
The FPGA provides the DCLK signal. This signal provides the timing for the serial interface.
The data presented on the DATA0 pin is latched to the EPCQ-L device on the rising edge of
the DCLK signal. The data on the DATA pin changes after the falling edge of the DCLK signal
and is latched in to the FPGA on the next falling edge of the DCLK signal.
DATA0
I/O For AS x1 mode, use this pin as an input signal pin to write or program the EPCQ-L device.
During write or program operations, the data is latched on the rising edge of the DCLK
signal.
For AS x4 mode, use this pin as an I/O signal pin. During write or program operations, this
pin acts as an input pin that serially transfers data into the EPCQ-L device. The data is
latched on the rising edge of the DCLK signal. During read or configuration operations, this
pin acts as an output signal pin that serially transfers data out of the EPCQ-L device to the
FPGA. The data is shifted out on the falling edge of the DCLK signal.
During the extended quad input fast write bytes operation, this pin acts as an input pin that
serially transfers data into the EPCQ-L device. The data is latched on the rising edge of the
DCLK signal. During extended quad input fast read operation, this pin acts as an output
signal pin that serially transfers data out of the EPCQ-L device to the FPGA. The data is
shifted out on the falling edge of the DCLK signal.
DATA1
I/O For AS x1 mode, use this pin as an output signal pin that serially transfers data out of the
EPCQ-L device to the FPGA during read or configuration operations. For AS x4 mode, use
this pin as an I/O signal pin. The transition of the signal is on the falling edge of the DCLK
signal.
During the extended quad input fast write bytes operation, this pin acts as an input signal
pin that serially transfers data into the EPCQ-L device. The data is latched on the rising
edge of the DCLK signal.
During extended quad input fast read operation, this pin acts as an output signal pin that
serially transfer data out of the EPCQ-L device to the FPGA. The data is shifted out on the
falling edge of the DCLK signal. During read, configuration, or program operations, you can
enable the EPCQ-L device by pulling the nCS signal low.
DATA2
I/O For AS x1 mode, this pin must connect to a 1.8-V power supply.
For AS x4 mode, use this pin as an output signal that serially transfers data out of the
EPCQ-L device to the FPGA during read or configuration operations. The transition of the
signal is on the falling edge of the DCLK signal.
During the extended quad input fast write bytes operation, this pin acts as an input pin that
serially transfers data into the EPCQ-L device. The data is latched on the rising edge of the
DCLK signal. During the extended quad input fast read operation, this pin acts as an output
signal pin that serially transfers data out of the EPCQ-L device to the FPGA. The data is
shifted out on the falling edge of the DCLK signal.
DATA3
I/O For AS x1 mode, this pin must connect to a 1.8-V power supply.
For AS x4 mode, use this pin as an output signal that serially transfers data out of the
EPCQ-L device to the FPGA during read or configuration operations. The transition of the
signal is on the falling edge of the DCLK signal.
continued...
EPCQ-L Serial Configuration Devices Datasheet
CF52013 | 2018.05.18
EPCQ-L Serial Configuration Devices Datasheet
7
