12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
07/22/09
IS64WV3216BLL
IS61WV3216BLL
DATA UNDEFINED
t
WC
ADDRESS 1 ADDRESS 2
t
WC
HIGH-Z
t
PBW
WORD 1
LOW
WORD 2
UB_CEWR4.eps
t
HD
t
SA
t
HZWE
ADDRESS
CE
UB, LB
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
t
PBW
DATA
IN
VALID
t
SD
t
HD
t
SA
t
HA
t
HA
WRITE CYCLE NO. 4
(LB, UB Controlled,Back-to-BackWrite)
(1,3)
Notes:
1. TheinternalWritetimeisdenedbytheoverlapofCE = Low, UB and/or LB = Low, and WE=LOW.Allsignalsmustbe
invalidstatestoinitiateaWrite,butanycanbedeassertedtoterminatetheWrite.The
t s A , t H A , t s d , and t H d timing is refer-
enced to the rising or falling edge of the signal that terminates the Write.
2. TestedwithOEHIGHforaminimumof4nsbeforeWE=LOWtoplacetheI/OinaHIGH-Zstate.
3. WEmaybeheldLOWacrossmanyaddresscyclesandtheLB, UB pins can be used to control the Write function.