LT3763
20
3763fb
For more information www.linear.com/LT3763
applicaTions inForMaTion
Figure 11. PWM Driver Operation
clock, please be aware that there will be a fixed delay from
the input clock edge to the edge of the signal at the SW pin.
The SYNC pin must be grounded if the synchronization to
an external clock is not required. When SYNC is grounded,
the switching frequency is determined by the resistor R
T
.
PWM Driver
The LT3763 includes a PWM driver for users who want to
control the dimming of LEDs connected to the output. The
driver will pull up the gate of an external N-channel MOSFET
connected to the PWM_OUT pin when the voltage at the
PWM pin rises above 2.175V and pull down the gate when
the voltage falls below 1.5V. When V
PWM
is lower than 1.5V,
switching is terminated and V
C
is disconnected from the
current regulation amplifier. When V
PWM
is above 2.175V,
the inductor current is regulated to the current programmed
by the voltage at the CTRL1, CTRL2, or FBIN pins.
The pull-up driver impedance is 2.2Ω, and the pull-down
driver impedance is 0.9Ω. The PWM dimming pulse-width
should be longer than two switching cycles.
When the PWM functionality is not desired, the PWM pin
should be tied to INTV
CC
so as not to disable switching.
PWM MOSFET Selection
The rated V
DS
for the PWM MOSFET need only be higher
than the maximum output voltage. Although this permits a
MOSFET choice with a smaller Q
G
specification than that of
the switching MOSFETs, it will have little effect on efficiency,
because the PWM switching frequency will be much lower
than that of the switching MOSFETs. Power lost charging the
gate of the PWM MOSFET will naturally be much lower than
the power lost charging the switching MOSFETs. R
DS(ON)
conduction losses in the PWM MOSFET will also be much
smaller if the duty cycle of the PWM signal is very low.
Like the drivers for the switching MOSFETs, the PWM
driver draws power from the INTV
CC
pin, and the choice
of MOSFET should follow the same recommendations for
threshold voltage (less than 2V) and rated V
GS
(at least 7V).
Thermal Shutdown
The internal thermal shutdown within the LT3763 engages
at 165°C and terminates switching and discharges the
soft-start capacitor. When the part has cooled to 160°C,
the internal reset is cleared and the soft-start capacitor is
allowed to charge.
Shutdown and UVLO
The LT3763 has an internal UVLO that terminates switch
-
ing, resets all synchronous logic, and discharges the soft-
start capacitor for input voltages below 4V. The LT3763
also has a precision shutdown at 1.52V on the EN/UVLO
pin. Partial shutdown occurs at 1.52V and full shutdown
is guaranteed below 0.5V with less than 2µA I
Q
in the full
shutdown state. Below 1.52V, an internal current source
provides 5µA of pull-down current to allow for program
-
mable UVLO hysteresis. The following equations determine
the voltage-divider resistors for programming the UVLO
voltage and hysteresis as configured in Figure 12.
R2=
HYST
5µA
–
UVLO
51µA
R1=
1.52V •R2
V
UVLO
–1.52V
PWM Operation
When the voltage at PWM is low, all switching of the high
and low side MOSFETS is terminated, and the inductor
current will decrease to zero. After PWM increases above
the logic threshold, the inductor current ramps up to the
regulated value. The ramp time, t
D
, can be estimated using
the following equation:
t
D
=
O
V
IN
– V
O
which assumes that the output capacitor does not discharge
significantly in the time that PWM is low.
–
+
OUT
PWM_OUT
PWM
1.5V
