LTC3809-1
19
38091fc
If the duty cycle falls below what can be accommodated
by the minimum on-time, the LTC3809-1 will begin to skip
cycles (unless forced continuous mode is selected). The
output voltage will continue to be regulated, but the ripple
current and ripple voltage will increase. The minimum on-
time for the LTC3809-1 is typically about 210ns. However,
as the peak sense voltage (I
L(PEAK)
• R
DS(ON)
) decreases,
the minimum on-time gradually increases up to about
260ns. This is of particular concern in forced continuous
applications with low ripple current at light loads. If forced
continuous mode is selected and the duty cycle falls below
the minimum on time requirement, the output will be
regulated by overvoltage protection.
Effi ciency Considerations
The effi ciency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting effi ciency and which change would produce the
most improvement. Effi ciency can be expressed as:
Effi ciency = 100% – (L1 + L2 + L3 + …)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of
the losses in LTC3809-1 circuits: 1) LTC3809-1 DC bias
current, 2) MOSFET gate-charge current, 3) I
2
R losses
and 4) transition losses.
1) The V
IN
(pin) current is the DC supply current, given
in the Electrical Characteristics, which excludes MOSFET
driver currents. V
IN
current results in a small loss that
increases with V
IN
.
2) MOSFET gate-charge current results from switching
the gate capacitance of the power MOSFET. Each time a
MOSFET gate is switched from low to high to low again,
a packet of charge dQ moves from V
IN
to ground. The
resulting dQ/dt is a current out of V
IN
, which is typically
much larger than the DC supply current. In continuous
mode, I
GATECHG
= f • Q
P
.
APPLICATIONS INFORMATION
3) I
2
R losses are calculated from the DC resistances of the
MOSFETs, inductor and/or sense resistor. In continuous
mode, the average output current fl ows through L but
is “chopped” between the top P-channel MOSFET and
the bottom N-channel MOSFET. The MOSFET R
DS(ON)
multiplied by duty cycle can be summed with the resistance
of L to obtain I
2
R losses.
4) Transition losses apply to the external MOSFET and
increase with higher operating frequencies and input
voltages. Transition losses can be estimated from:
Transition Loss = 2 • V
IN
2
• I
O(MAX)
• C
RSS
• f
Other losses, including C
IN
and C
OUT
ESR dissipative losses
and inductor core losses, generally account for less than
2% total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to (ΔI
LOAD
) • (ESR), where ESR is the effective se-
ries resistance of C
OUT
. ΔI
LOAD
also begins to charge or
discharge C
OUT
generating a feedback error signal used
by the regulator to return V
OUT
to its steady-state value.
During this recovery time, V
OUT
can be monitored for
overshoot or ringing that would indicate a stability problem.
OPTI-LOOP compensation allows the transient response
to be optimized over a wide range of output capacitance
and ESR values.
The I
TH
series R
C
-C
C
fi lter (see Functional Diagram) sets
the dominant pole-zero loop compensation.
The I
TH
external components showed in the fi gure on the
fi rst page of this data sheet will provide adequate compen-
sation for most applications. The values can be modifi ed
slightly (from 0.2 to 5 times their suggested values) to
optimize transient response once the fi nal PC layout is done
and the particular output capacitor type and value have
been determined. The output capacitor needs to be decided
upon because the various types and values determine the
loop feedback factor gain and phase. An output current
