CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Document #: 38-06078 Rev. *B Page 13 of 18
Note
34. If t
PS
is violated, the busy signal is asserted on one side or the other, but there is no guarantee to which side BUSY is asserted.
Switching Waveforms
(continued)
ADDRESS MATCH
t
PS
t
BLC
t
BHC
ADDRESS MATCH
t
PS
t
BLC
t
BHC
CE
R
ValidFirst:
ADDRESS
L,R
BUSY
R
CE
L
CE
R
BUSY
L
CE
R
CE
L
ADDRESS
L,R
Figure 13. Busy Timing Diagram No. 1 (CE Arbitration)
[34]
CE
L
Valid First:
ADDRESS MATCH
t
PS
ADDRESS
L
BUSY
R
ADDRESS MISMATCH
t
RC
or t
WC
t
BLA
t
BHA
ADDRESS
R
ADDRESS MATCH ADDRESS MISMATCH
t
PS
ADDRESS
L
BUSY
L
t
RC
or t
WC
t
BLA
t
BHA
ADDRESS
R
Right AddressValid First:
Figure 14. Busy Timing Diagram No. 2 (Address Arbitration)
[34]
Left Address Valid First:
[+] Feedback
CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Document #: 38-06078 Rev. *B Page 14 of 18
Figure 15. Interrupt Timing Diagrams
Notes
35. t
HA
depends on which enable pin (CE
L
or R/W
L
) is deasserted first.
36. t
INS
or t
INR
depends on which enable pin (CE
L
or R/W
L
) is asserted last.
Switching Waveforms
(continued)
WRITE 7FFF (FFFF for CY7C028V/38V)
t
WC
Right Side Clears INT
R
:
t
HA
READ 7FFF
t
RC
t
INR
WRITE 7FFE (FFFE for CY7C028V/38V)
t
WC
Right SideSets INT
L
:
Left Side Sets INT
R
:
Left SideClears INT
L
:
READ 7FFE
t
INR
t
RC
ADDRESS
R
CE
L
R/W
L
INT
L
OE
L
ADDRESS
R
R/W
R
CE
R
INT
L
ADDRESS
R
CE
R
R/W
R
INT
R
OE
R
ADDRESS
L
R/W
L
CE
L
INT
R
t
INS
t
HA
t
INS
(FFFF for CY7C028V/38V)
(FFFF for CY7C028V/38V)
[35]
[36]
[36]
[36]
[35]
[36]
[+] Feedback
CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Document #: 38-06078 Rev. *B Page 15 of 18
Table 1. Non-Contending Read/Write
Inputs Outputs
CE R/W OE UB LB SEM I/O
9
I/O
17
I/O
0
I/O
8
Operation
H X X X X H High Z High Z Deselected: Power Down
X X X H H H High Z High Z Deselected: Power Down
L L X L H H Data In High Z Write to Upper Byte Only
L L X H L H High Z Data In Write to Lower Byte Only
L L X L L H Data In Data In Write to Both Bytes
L H L L H H Data Out High Z Read Upper Byte Only
L H L H L H High Z Data Out Read Lower Byte Only
L H L L L H Data Out Data Out Read Both Bytes
X X H X X X High Z High Z Outputs Disabled
H H L X X L Data Out Data Out Read Data in Semaphore Flag
X H L H H L Data Out Data Out Read Data in Semaphore Flag
H X X X L Data In Data In Write D
IN0
into Semaphore Flag
X X H H L Data In Data In Write D
IN0
into Semaphore Flag
L X X L X L Not Allowed
L X X X L L Not Allowed
Table 2. Interrupt Operation Example (assumes BUSY
L
=BUSY
R
=HIGH)
[37]
Left Port Right Port
Function R/W
L
CE
L
OE
L
A
0L–14L
INT
L
R/W
R
CE
R
OE
R
A
0R–14R
INT
R
Set Right INT
R
Flag L L X 7FFF X X X X X L
[39]
Reset Right INT
R
FlagXXXXXXLL7FFFH
[38]
Set Left INT
L
Flag XXX X L
[38]
LLX 7FFE X
Reset Left INT
L
Flag X L L 7FFE H
[39]
XXX X X
Table 3. Semaphore Operation Example
Function I/O
0
I/O
17
Left I/O
0
I/O
17
Right Status
No action 1 1 Semaphore free
Left port writes 0 to semaphore 0 1 Left port has semaphore token
Right port writes 0 to semaphore 0 1 No change. Right side has no write access to semaphore
Left port writes 1 to semaphore 1 0 Right port obtains semaphore token
Left port writes 0 to semaphore 1 0 No change. Left port has no write access to semaphore
Right port writes 1 to semaphore 0 1 Left port obtains semaphore token
Left port writes 1 to semaphore 1 1 Semaphore free
Right port writes 0 to semaphore 1 0 Right port has semaphore token
Right port writes 1 to semaphore 1 1 Semaphore free
Left port writes 0 to semaphore 0 1 Left port has semaphore token
Left port writes 1 to semaphore 1 1 Semaphore free
Notes
37. A
0L–15L
and A
0R–15R
,FFFF/FFFE for the CY7C028V/038V.
38. If BUSY
R
=L, then no change.
39. If BUSY
L
=L, then no change.
[+] Feedback

CY7C038V-15AC

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
IC SRAM 1.152M PARALLEL 100TQFP
Lifecycle:
New from this manufacturer.
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