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CY7C038V-15AC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Document #: 38-06078 Rev. *B Page 7 of 18
Figure 3. AC Test Loads and Waveforms
3.0V
GND
90%
90%
10%
3ns
3
ns
10%
ALL INPUTPULSES
(a) Normal Load (Load
1)
R1 = 590Ω
3.3V
OUTPUT
R2 = 435Ω
C= 30
pF
V
TH
=1.4V
OUTPUT
C= 30 pF
(b) Thévenin Equivalent (Load 1)
(c) Three-State Delay(Load 2)
R1 = 590Ω
R2 = 435Ω
3.3V
OUTPUT
C= 5pF
R
TH
= 250Ω
≤
≤
including scope and jig)
(Used for t
LZ
, t
HZ
, t
HZWE
, & t
LZWE
Switching Characteristics
Over the Operating Range
[6]
Parameter Description
CY7C027V/027VN/027AV/028V/
CY7C037V/037AV/038V
Unit
-15 -20 -25
Min Max Min Max Min Max
Read Cycle
t
RC
Read Cycle Time 15 20 25 ns
t
AA
Address to Data Valid 15 20 25 ns
t
OHA
Output Hold From Address Change 3 3 3 ns
t
ACE
[7]
CE LOW to Data Valid 15 20 25 ns
t
DOE
OE LOW to Data Valid 10 12 13 ns
t
LZOE
[8, 9, 10]
OE LOW to Low Z 3 3 3 ns
t
HZOE
[8, 9, 10]
OE HIGH to High Z 10 12 15 ns
t
LZCE
[8, 9, 10]
CE LOW to Low Z 3 3 3 ns
t
HZCE
[8, 9, 10]
CE HIGH to High Z 10 12 15 ns
t
PU
[10]
CE LOW to Power Up 0 0 0 ns
t
PD
[10]
CE HIGH to Power Down 15 20 25 ns
t
ABE
[7]
Byte Enable Access Time 15 20 25 ns
Write Cycle
t
WC
Write Cycle Time 15 20 25 ns
t
SCE
[7]
CE LOW to Write End 12 16 20 ns
t
AW
Address Valid to Write End 12 16 20 ns
t
HA
Address Hold From Write End 0 0 0 ns
t
SA
[7]
Address Setup to Write Start 0 0 0 ns
t
PWE
Write Pulse Width 12 17 22 ns
t
SD
Data Setup to Write End 10 12 15 ns
Notes
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I
OI
/I
OH
and 30 pF load capacitance.
7. To access RAM, CE
=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire t
SCE
time.
8. At any given temperature and voltage condition for any given device, t
HZCE
is less than t
LZCE
and t
HZOE
is less than t
LZOE
.
9. Test conditions used are Load 2.
10. This parameter is guaranteed by design, but it is not production tested. For information on port-to-port delay through RAM cells from writing port to reading port,
refer to Figure 11.
[+] Feedback
CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Document #: 38-06078 Rev. *B Page 8 of 18
Data Retention Mode
The CY7C027V/027VN/027AV/028V and
CY7037V/037AV/038V are designed with battery backup in
mind. Data retention voltage and supply current are guaranteed
over temperature. The following rules ensure data retention:
1. Chip enable (CE) must be held HIGH during data retention, within
V
CC
to V
CC
– 0.2V.
2. CE
must be kept between V
CC
– 0.2V and 70% of V
CC
during
the power up and power down transitions.
3. The RAM can begin operation >t
RC
after V
CC
reaches the mini-
mum operating voltage (3.0 volts).
t
HD
Data Hold From Write End 0 0 0 ns
t
HZWE
[9, 10]
R/W LOW to High Z 10 12 15 ns
t
LZWE
[9 ,10]
R/W HIGH to Low Z 3 3 3 ns
t
WDD
[36]
Write Pulse to Data Delay 30 40 50 ns
t
DDD
[36]
Write Data Valid to Read Data Valid 25 30 35 ns
Busy Timing
[11]
t
BLA
BUSY LOW from Address Match 15 20 20 ns
t
BHA
BUSY HIGH from Address Mismatch 15 20 20 ns
t
BLC
BUSY LOW from CE LOW 15 20 20 ns
t
BHC
BUSY HIGH from CE HIGH 15 16 17 ns
t
PS
Port Setup for Priority 5 5 5 ns
t
WB
R/W HIGH after BUSY (Slave) 0 0 0 ns
t
WH
R/W HIGH after BUSY HIGH (Slave) 13 15 17 ns
t
BDD
[13]
BUSY HIGH to Data Valid 15 20 25 ns
Interrupt Timing
[11]
t
INS
INT Set Time 15 20 20 ns
t
INR
INT Reset Time 15 20 20 ns
Semaphore Timing
t
SOP
SEM Flag Update Pulse (OE or SEM)101012ns
t
SWRD
SEM Flag Write to Read Time 5 5 5 ns
t
SPS
SEM Flag Contention Window 5 5 5 ns
t
SAA
SEM Address Access Time 15 20 25 ns
Switching Characteristics
Over the Operating Range
[6]
(continued)
Parameter Description
CY7C027V/027VN/027AV/028V/
CY7C037V/037AV/038V
Unit
-15 -20 -25
Min Max Min Max Min Max
Timing
Parameter Test Conditions
[14]
Max Unit
ICC
DR1
At VCC
DR
= 2V 50 μA
Notes
11. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Figure 11 waveform.
12. Test conditions used are Load 1.
13. t
BDD
is a calculated parameter and is the greater of t
WDD
–t
PWE
(actual) or t
DDD
–t
SD
(actual).
14. CE
= V
CC
, V
in
= GND to V
CC
, T
A
= 25° C. This parameter is guaranteed but not tested.
[+] Feedback
CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Document #: 38-06078 Rev. *B Page 9 of 18
Switching Waveforms
Notes
15. R/W
is HIGH for read cycles.
16. Device is continuously selected CE = V
IL
and UB or LB = V
IL
. This waveform cannot be used for semaphore reads.
17. OE
= V
IL
.
18. Address valid prior to or coincident with CE
transition LOW.
19. To access RAM, CE = V
IL
, UB or LB = V
IL
, SEM = V
IH
. To access semaphore, CE = V
IH
, SEM = V
IL
.
t
RC
t
AA
t
OHA
DATA VALIDPREVIOUS DATA VALID
DATA OUT
ADDRESS
t
OHA
Figure 4. Read Cycle No. 1 (Either Port Address Access)
[15, 16, 17]
t
ACE
t
LZOE
t
DOE
t
HZOE
t
HZCE
DATA VALID
t
LZCE
t
PU
t
PD
I
SB
I
CC
DATA OUT
OE
CE and
LB
or UB
CURRENT
Figure 5. Read Cycle No. 2 (Either Port CE/OE Access)
[15, 18, 19]
UB or LB
DATA OUT
t
RC
ADDRESS
t
AA
t
OHA
CE
t
LZCE
t
ABE
t
HZCE
t
HZCE
t
ACE
t
LZCE
Figure 6. Read Cycle No. 3 (Either Port)
[15, 17, 18, 19]
[+] Feedback
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

CY7C038V-15AC

Mfr. #:
Buy CY7C038V-15AC
Manufacturer:
Cypress Semiconductor
Description:
IC SRAM 1.152M PARALLEL 100TQFP
Lifecycle:
New from this manufacturer.
Delivery:
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