DMOS Dual Full-Bridge PWM Motor Driver
A3974
8
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
V
REG
. This internally generated supply voltage is used to oper-
ate the sink-side DMOS outputs. V
REG
is internally monitored
and in the case of a fault condition, the outputs of the device are
disabled. The V
REG
terminal should be decoupled with a 0.22 μF
capacitor to ground.
Charge Pump. The charge pump is used to generate a supply
voltage greater than V
BB
to drive the source-side DMOS gates.
A 0.22 μF ceramic capacitor should be connected between CP1
and CP2 for pumping purposes. A 0.22 μF ceramic capacitor
should be connected between V
CP
and V
BB
to act as a reservoir
to run the high-side DMOS devices. The CP voltage is internally
monitored and in the case of a fault condition, the outputs of the
device are disabled.
Shutdown. In the event of a fault due to excessive junction
temperature, or low voltage on CP or V
REG
, the outputs of the
device are disabled until the fault condition is removed. At
power up, or in the event of low V
DD
, the UVLO circuit disables
the drivers and resets the data in the serial port to all zeros.
Current Regulation. Load current is regulated by an inter-
nal fi xed off-time PWM control circuit. When the outputs of
the DMOS H-bridge are turned on, the current increases in the
motor winding until it reaches a trip value determined by the
external sense resistor (R
S
), the applied analog reference voltage
(V
REF
), and serial data bit D16:
When D16 = 0 ....................... I
TRIP
= V
REF
/10R
S
When D16 = 1 ....................... I
TRIP
= V
REF
/5R
S
At the trip point, the sense comparator resets the source-enable
latch, turning off the source driver (except in the case of low-
side only mode where the sink driver is turned off). The load
inductance then causes the current to recirculate for the serial-
port programmed fi xed off-time period. The current path during
recirculation is determined by the confi guration of slow/mixed-
decay mode (D17) and the synchronous rectifi cation control bits
(D11 and D12).
Sleep Mode. The input terminal SLEEP is dedicated to putting
the device into a minimum current draw mode. When asserted
FUNCTIONAL DESCRIPTION (continued)
low, the serial port will be reset to all zeros and all circuits will
be disabled.
PWM Timer Function. The PWM timer is programmable via
the serial port (bits D2 – D10) to provide fi xed off-time PWM
signals to the control circuitry. In mixed current-decay mode,
the fi rst portion of the off time operates in fast decay, until the
fast-decay time count is reached (serial bits D7 – D10), followed
by slow decay for the rest of the off-time period (bits D2 – D6).
If the fast-decay time is set longer than the off-time, the device
effectively operates in fast-decay mode. Bit D17 selects mixed
or slow decay.
Synchronous Rectifi cation. When a PWM off cycle is trig-
gered, either by an ENABLE chop command or internal fi xed
off-time cycle, load current will recirculate according to the
decay mode selected by the control logic. After a short crossover
delay, the A3974 synchronous rectifi cation feature will turn on
the appropriate MOSFET (or pair of MOSFETs for the mixed
decay portion of the off-time) during the current decay and ef-
fectively short out the body diodes with the low r
DS(on)
driver.
This will lower power dissipation signifi cantly and can eliminate
the need for external Schottky diodes.
Synchronous rectifi cation can be confi gured in active mode, pas-
sive mode, low side only, or disabled via the serial port (bits D11
and D12). The active mode prevents reversal of load current by
turning off synchronous rectifi cation when a zero current level
is detected. Passive mode will allow reversal of current but will
turn off the synchronous rectifi er circuit if the load current inver-
sion ramps up to the current limit set by
V
REF
/10R
S
(when D16 = 0) or V
REF
/5R
S
(when D16 = 1).
Low side only mode will switch the low-side MOSFETs on dur-
ing the off time to short out the current path through the MOS-
FET body diode. With this setting, the high-side MOSFETs will
not synchronously rectify so four external diodes from output
to supply are recommended. This mode is intended for use with
high-power applications where it is desired to save the expense
of two external diodes per bridge. In this mode, the sink-side
MOSFETs are chopped during the PWM off time. In all other
cases, the source-side MOSFETs are chopped in response to a
PWM OFF command.
