MAX5874EGK+TD Datasheet MAX5874EGK+D, MAX5874EGK+TD | P10-P12

MAX5874

14-Bit, 200Msps, High-Dynamic-Performance,

Dual DAC with CMOS Inputs

10 ______________________________________________________________________________________

Analog Outputs

(OUTIP, OUTIN, OUTQP, OUTQN)

Each MAX5874 DAC outputs two complementary cur-

rents (OUTIP/N, OUTQP/N) that operate in a single-

ended or differential configuration. A load resistor

converts these two output currents into complementary

single-ended output voltages. A transformer or a differ-

ential amplifier configuration converts the differential

voltage existing between OUTIP (OUTQP) and OUTIN

(OUTQN) to a single-ended voltage. If not using a

transformer, the recommended termination from the

output is a 25Ω termination resistor to ground and a

50Ω resistor between the outputs.

To generate a single-ended output, select OUTIP (or

OUTQP) as the output and connect OUTIN (or OUTQN)

to GND. SFDR degrades with single-ended operation.

Figure 3 displays a simplified diagram of the internal

output structure of the MAX5874.

Clock Inputs (CLKP, CLKN)

The MAX5874 features flexible differential clock inputs

(CLKP, CLKN) operating from a separate supply

(AV

CLK

) to achieve the optimum jitter performance.

Drive the differential clock inputs from a single-ended

or a differential clock source. For single-ended opera-

tion, drive CLKP with a logic source and bypass CLKN

to GND with a 0.1µF capacitor.

CLKP and CLKN are internally biased to AV

CLK

/ 2. This

facilitates the AC-coupling of clock sources directly to

the device without external resistors to define the DC

level. The dynamic input resistance from CLKP and

CLKN to ground is > 5kΩ.

Data Timing Relationship

Figure 4 displays the timing relationship between digital

CMOS data, clock, and output signals. The MAX5874

features a 1.5ns hold, a -1.2ns setup, and a 1.1ns propa-

gation delay time. A nine (eight)-clock-cycle latency

exists between CLKP/CLKN and OUTIP/OUTIN

(OUTQP/OUTQN) when operating in single-port (inter-

leaved) mode. In dual-port (parallel) mode, the clock

latency is 5.5 clock cycles for both channels. Table 2

shows the DAC output codes.

LATCH

XOR/

DECODE

LATCH

CMOS

RECEIVER

LATCH

LATCH DAC

OUTIP

OUTIN

LATCH

XOR/

DECODE

LATCH LATCH DAC

OUTQP

OUTQN

FSADJ

TORB

SELIQ

XOR

CLK

CLKN

GND

CLKP

CLK

INTERFACE

DATA13–

DATA0

1.2V

REFERENCE

POWER-DOWN

BLOCK

REFIO

DACREF

PD GND

DD1.8

DD3.3

GND AV

DD1.8

DD3.3

DORI

MAX5874

Figure 1. MAX5874 High-Performance, 14-Bit, Dual Current-Steering DAC

MAX5874

14-Bit, 200Msps, High-Dynamic-Performance,

Dual DAC with CMOS Inputs

______________________________________________________________________________________ 11

CMOS-Compatible Digital Inputs

Input Data Format Select (TORB,

DORI

)

The TORB input selects between two’s-complement or

binary digital input data. Set TORB to a CMOS-logic-

high level to indicate a two’s-complement input format.

Set TORB to a CMOS-logic-low level to indicate a binary

input format.

The DORI input selects between a dual-port (parallel) or

single-port (interleaved) DAC. Set DORI high to configure

the MAX5874 as a dual-port DAC. Set DORI low to con-

figure the MAX5874 as a single-port DAC. In dual-port

mode, connect SELIQ to ground.

CMOS DAC Inputs (A13/B13–A0/B0, XOR, SELIQ)

The MAX5874 latches input data on the rising edge of

the clock in a user-selectable two’s-complement or

binary format. A logic-high voltage on TORB selects

two’s-complement and a logic-low selects offset

binary format.

The MAX5874 includes a single-ended, CMOS-compati-

ble XOR input. Input data (all bits) are compared with the

bit applied to XOR through exclusive-OR gates. Pulling

XOR high inverts the input data. Pulling XOR low leaves

the input data noninverted. By applying a previously

encoded pseudo-random bit stream to the data input and

applying decoding to XOR, the digital input data can be

decorrelated from the DAC output, allowing for the trou-

bleshooting of possible spurious or harmonic distortion

degradation due to digital feedthrough on the printed

circuit board (PCB).

A13/B13–A0/B0, XOR, and SELIQ are latched on the ris-

ing edge of the clock. In single-port mode (DORI pulled

low) a logic-high signal on SELIQ directs the B13–B0

data onto the I-DAC inputs. A logic-low signal at SELIQ

directs data to the Q-DAC inputs. In dual-port (parallel)

mode (DORI pulled high), data on pins A13–A0 are

directed onto the Q-DAC inputs and B13–B0 are directed

onto the I-DAC inputs.

Power-Down Operation (PD)

The MAX5874 also features an active-high power-

down mode that reduces the DAC’s digital current

consumption from 22mA to less than 2µA and the ana-

log current consumption from 77mA to less than 2µA.

Set PD high to power down the MAX5874. Set PD low

for normal operation.

When powered down, the power consumption of the

MAX5874 is reduced to less than 14µW. The MAX5874

requires 10ms to wake up from power-down and enter a

fully operational state. The PD integrated pulldown resistor

activates the MAX5874 if PD is left floating.

OUTIP

OUTIN

1.2V

REFERENCE

CURRENT-SOURCE

ARRAY DAC

REFIO

FSADJ

SET

REF

10kΩ

DACREF

1µF

REF

= V

REFIO

/ R

SET

Figure 2. Reference Architecture, Internal Reference

Configuration

OUT

OUTIN OUTIP

CURRENT

SOURCES

CURRENT

SWITCHES

Figure 3. Simplified Analog Output Structure

Table 2. DAC Output Code Table

DIGITAL INPUT CODE

OFFSET

BINARY

TWO’S

COMPLEMENT

OUT_P OUT_N

00 0000 0000 0000 10 0000 0000 0000 0 I

OUTFS

01 1111 1111 1111 00 0000 0000 0000 I

OUTFS

/ 2 I

OUTFS

/ 2

11 1111 1111 1111 01 1111 1111 1111 I

OUTFS

MAX5874

14-Bit, 200Msps, High-Dynamic-Performance,

Dual DAC with CMOS Inputs

12 ______________________________________________________________________________________

Applications Information

CLK Interface

The MAX5874 features a flexible differential clock input

(CLKP, CLKN) with a separate supply (AV

CLK

) to

achieve optimum jitter performance. Use an ultra-low

jitter clock to achieve the required noise density. Clock

jitter must be less than 0.5ps

RMS

for meeting the speci-

fied noise density. For that reason, the CLKP/CLKN

input source must be designed carefully. The differen-

tial clock (CLKN and CLKP) input can be driven from a

single-ended or a differential clock source. Differential

clock drive is required to achieve the best dynamic

performance from the DAC. For single-ended opera-

tion, drive CLKP with a low-noise source and bypass

CLKN to GND with a 0.1µF capacitor.

Figure 5 shows a convenient and quick way to apply a

differential signal created from a single-ended source

(e.g., HP/AGILENT 8644B signal generator) and a wide-

band transformer. Alternatively, these inputs can be

driven from a CMOS-compatible clock source; however, it

is recommended to use sinewave or AC-coupled differ-

ential ECL/PECL drive for best dynamic performance.

DATA13–DATA0, XOR

CLK

DAC OUTPUT

N - 1 N N + 1 N + 2

N - 5

N - 4

N - 3

N - 2

N - 6

SELIQ

CLK

DATA

I0 Q2I2Q1I1 I3 Q3Q0

I OUT

Q OUT

I - 5

I - 4 I - 2

I - 3

I - 6

Q - 6

Q - 5

Q - 4

Q - 3 Q - 2

(a) DUAL-PORT (PARALLEL) TIMING DIAGRAM

(b) SINGLE-PORT (INTERLEAVED) TIMING DIAGRAM

Figure 4. Timing Relationships Between Clock and Input Data for (a) Dual-Port (Parallel) Mode and (b) Single-Port (Interleaved) Mode

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

MAX5874EGK+TD

Mfr. #:

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Manufacturer:

Maxim Integrated

Description:

Digital to Analog Converters - DAC 14-Bit 2Ch 200Msps DAC

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MAX5874EGK+TD

MAX5874EGK+TD

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