MAX5874
14-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
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Detailed Description
Architecture
The MAX5874 high-performance, 14-bit, dual current-
steering DAC (Figure 1) operates with DAC update rates
up to 200Msps. The converter consists of input registers
and a demultiplexer for single-port (interleaved) mode,
followed by a current-steering array. During operation in
interleaved mode, the input data registers demultiplex
the single-port data bus. The current-steering array gen-
erates differential full-scale currents in the 2mA to 20mA
range. An internal current-switching network, in combina-
tion with external 50Ω termination resistors, converts the
differential output currents into dual differential output
voltages with a 0.1V to 1V peak-to-peak output voltage
range. An integrated 1.2V bandgap reference, control
amplifier, and user-selectable external resistor determine
the data converter’s full-scale output range.
Reference Architecture and Operation
The MAX5874 supports operation with the internal 1.2V
bandgap reference or an external reference voltage
source. REFIO serves as the input for an external, low-
impedance reference source. REFIO also serves as a
reference output when the DAC operates in internal ref-
erence mode. For stable operation with the internal ref-
erence, decouple REFIO to GND with a 1µF capacitor.
Due to its limited output-drive capability, buffer REFIO
with an external amplifier when driving large
external loads.
The MAX5874’s reference circuit (Figure 2) employs a
control amplifier to regulate the full-scale current
I
OUTFS
for the differential current outputs of the DAC.
Calculate the full-scale output current as follows:
where I
OUTFS
is the full-scale output current of the
DAC. R
SET
(located between FSADJ and DACREF)
determines the amplifier’s full-scale output current for
the DAC. See Table 1 for a matrix of different I
OUTFS
and R
SET
selections.
DAC Exclusive-OR Select Input. Set XOR low to allow the data stream to pass unchanged to the
DAC input. Set XOR high to invert the input data into the DAC. If unused, connect XOR to GND.
DAC Select Input. Set SELIQ low to direct data into the Q-DAC inputs. Set SELIQ high to direct
data into the I-DAC inputs. If unused, connect SELIQ to GND. SELIQ’s logic state is only valid in
single-port (interleaved) mode.
Data Bits B13–B0. In dual-port mode, data is directed to the I-DAC. In single-port mode, the state
of SELIQ determines where the data bits are directed.
Digital Supply Voltage. Accepts a 1.71V to 1.89V supply voltage range. Bypass with a 0.1µF
capacitor to GND.
Data Bits A13–A7. In dual-port mode, data is directed to the Q-DAC. In single-port mode, data
bits are not used. Connect bits A13–A7 to GND in single-port mode.
