IDT1337
REAL-TIME CLOCK WITH I
2
C SERIAL INTERFACE RTC
IDT™
REAL-TIME CLOCK WITH I
2
C SERIAL INTERFACE 10
IDT1337 REV H 120208
Data Transfer on I
2
C Serial Bus
Depending upon the state of the R/W bit, two types of data
transfer are possible:
1) Data transfer from a master transmitter to a slave
receiver. The first byte transmitted by the master is the
slave address. Next follows a number of data bytes. The
slave returns an acknowledge bit after each received byte.
Data is transferred with the most significant bit (MSB) first.
2) Data transfer from a slave transmitter to a master
receiver. The first byte (the slave address) is transmitted by
the master. The slave then returns an acknowledge bit,
followed by the slave transmitting a number of data bytes.
The master returns an acknowledge bit after all received
bytes other than the last byte. At the end of the last received
byte, a “not acknowledge” is returned. The master device
generates all of the serial clock pulses and the START and
STOP conditions. A transfer is ended with a STOP condition
or with a repeated START condition. Since a repeated
START condition is also the beginning of the next serial
transfer, the bus is not released. Data is transferred with the
most significant bit (MSB) first.
The IDT1337 can operate in the following two modes:
1) Slave Receiver Mode (Write Mode): Serial data and
clock are received through SDA and SCL. After each byte is
received an acknowledge bit is transmitted. START and
STOP conditions are recognized as the beginning and end
of a serial transfer. Address recognition is performed by
hardware after reception of the slave address and direction
bit (see the “Data Write–Slave Receiver Mode” figure). The
slave address byte is the first byte received after the START
condition is generated by the master. The slave address
byte contains the 7-bit IDT1337 address, which is 1101000,
followed by the direction bit (R/W
), which is 0 for a write.
After receiving and decoding the slave address byte the
device outputs an acknowledge on the SDA line. After the
IDT1337 acknowledges the slave address + write bit, the
master transmits a register address to the IDT1337. This
sets the register pointer on the IDT1337. The master may
then transmit zero or more bytes of data, with the IDT1337
acknowledging each byte received. The address pointer
increments after each data byte is transferred. The master
generates a STOP condition to terminate the data write.
2) Slave Transmitter Mode (Read Mode): The first byte is
received and handled as in the slave receiver mode.
However, in this mode, the direction bit indicates that the
transfer direction is reversed. Serial data is transmitted on
SDA by the IDT1337 while the serial clock is input on SCL.
START and STOP conditions are recognized as the
beginning and end of a serial transfer (see the “Data
Read–Slave Transmitter Mode” figure). The slave address
byte is the first byte received after the START condition is
generated by the master. The slave address byte contains
the 7-bit IDT1337 address, which is 1101000, followed by
the direction bit (R/W
), which is 1 for a read. After receiving
and decoding the slave address byte the slave outputs an
acknowledge on the SDA line. The IDT1337 then begins to
transmit data starting with the register address pointed to by
the register pointer. If the register pointer is not written to
