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1337DCGI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
IDT1337
REA LTIME CLOCK WITH SERIAL INTERFACE RTC
IDT™
REAL-TIME CLOCK WITH I
2
C SERIAL INTERFACE 13
IDT1337 REV H 120208
DC Electrical Characteristics
Unless stated otherwise, VCC = 1.3 V to 1.8 V, Ambient Temperature -40 to +85° C, Note 1
AC Electrical Characteristics
Unless stated otherwise, VCC = 1.8 V to 5.5 V, Ambient Temperature -40 to +85° C, Note 1
Parameter Symbol Conditions Min. Typ. Max. Units
Timekeeper Current (Oscillator
Enabled)
I
CCTOSC
Notes 5, 7, 8, 9 425 600 nA
Data-Retention Current (Oscillator
Disabled)
I
CCTDDR
Notes 5, 9 100 nA
Parameter Symbol Conditions Min. Typ. Max. Units
SCL Clock Frequency f
SCL
Fast Mode 100 400 kHz
Standard Mode 0 100
Bus Free Time Between a STOP and
START Condition
t
BUF
Fast Mode 1.3 µs
Standard Mode 4.7
Hold Time (Repeated) START
Condition, Note 10
t
HD:STA
Fast Mode 0.6 µs
Standard Mode 4.0
Low Period of SCL Clock t
LOW
Fast Mode 1.3 µs
Standard Mode 4.7
High Period of SCL Clock t
HIGH
Fast Mode 0.6 µs
Standard Mode 4.0
Setup Time for a Repeated START
Condition
t
SU:STA
Fast Mode 0.6 µs
Standard Mode 4.7
Data Hold Time, Notes 11, 12 t
HD:DAT
Fast Mode 0 0.9 µs
Standard Mode 0
Data Setup Time, Note 13 t
SU:DAT
Fast Mode 100 ns
Standard Mode 250
Rise Time of Both SDA and SCL
Signals, Note 14
t
R
Fast Mode 20 + 0.1C
B
300 ns
Standard Mode 20 + 0.1C
B
1000
Fall Time of Both SDA and SCL Signals,
Note 14
t
F
Fast Mode 20 + 0.1C
B
300 ns
Standard Mode 20 + 0.1C
B
300
Setup Time for STOP Condition t
SU:STO
Fast Mode 0.6 µs
Standard Mode 4.0
Capacitive Load for Each Bus Line,
Note 14
C
B
400 pF
I/O Capacitance (SDA, SCL) C
I/O
Note 15 10 pF
32.768 kHz Clock Accuracy with
External Crystal
TA=25°C
V
CC=3.3 V
±10 ppm
IDT1337
REAL-TIME CLOCK WITH I
2
C SERIAL INTERFACE RTC
IDT™
REAL-TIME CLOCK WITH I
2
C SERIAL INTERFACE 14
IDT1337 REV H 120208
Note 1: Limits at -40°C are guaranteed by design and are not production tested.
Note 2: SCL only.
Note 3: SDA, INTA
, and SQW/INTB.
Note 4: I
CCA
—SCL clocking at maximum frequency = 400 kHz, VIL = 0.0V, VIH = VCC.
Note 5: Specified with the I
2
C bus inactive, VIL = 0.0V, VIH = VCC.
Note 6: SQW enabled.
Note 7: Specified with the SQW function disabled by setting INTCN = 1.
Note 8: Using recommended crystal on X1 and X2.
Note 9: The device is fully accessible when 1.8 <
VCC < 5.5 V. Time and date are maintained when 1.3 V < VCC <
1.8 V.
Note 10: After this period, the first clock pulse is generated.
Note 11: A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
IHMIN
of
the SCL signal) to bridge the undefined region of the falling edge of SCL.
Note 12: The maximum t
HD:DAT
need only be met if the device does not stretch the LOW period (t
LOW
) of the SCL
signal.
Note 13: A fast-mode device can be used in a standard-mode system, but the requirement t
SU:DAT
> to 250 ns must
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such
a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t
R(MAX)
+
t
SU:DAT
= 1000 + 250 = 1250 ns before the SCL line is released.
Note 14: C
B
—total capacitance of one bus line in pF.
Note 15: Guaranteed by design. Not production tested.
32.768 kHz Clock Accuracy with
Internal Crystal
T
A=25°C
V
CC=3.3 V
(crystal accuracy
±20ppm)
±30 ppm
Parameter Symbol Conditions Min. Typ. Max. Units
IDT1337
REA LTIME CLOCK WITH SERIAL INTERFACE RTC
IDT™
REAL-TIME CLOCK WITH I
2
C SERIAL INTERFACE 15
IDT1337 REV H 120208
Timing Diagram
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

1337DCGI

Mfr. #:
Buy 1337DCGI
Manufacturer:
Description:
IC RTC CLK/CALENDAR I2C 8-SOIC
Lifecycle:
New from this manufacturer.
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