11
LTC1594L/LTC1598L
15948lfb
APPLICATIONS INFORMATION
WUU
U
Figure 2. LTC1594L/LTC1598L Operating Sequence Example: All Channels Off
CLK
EN D1
D2
t
CYC
Hi-Z
D
OUT
CH0 TO
CH7
D
IN
t
CONV
Hi-Z
t
suCS
NULL
BIT
D0
t
OFF
D0N‘T CARE
ADCIN =
MUXOUT
COM = GND
1594L/98L F02
DUMMY CONVERSION
CSMUX = CSADC = CS
break-before-make interval, t
OPEN
. After a delay of t
ON
(t
OFF
+ t
OPEN
), the selected channel is switched on,
allowing the ADC in the chip to acquire input signal and
start the conversion (see Figures 1 and 2). After 1 null bit,
the result of the conversion is output on the D
OUT
line.
The selected channel remains on, until the next falling
edge of CS. At the end of the data exchange, CS should
be brought high. This resets the LTC1594L/LTC1598L
and initiates the next data exchange.
D
IN1
D
IN2
D
OUT1
D
OUT2
CS
SHIFT MUX
ADDRESS IN
t
SMPL
+ 1 NULL BIT
SHIFT A/D CONVERSION
RESULT OUT
1594L/98L AI01
Break-Before-Make
The LTC1594L/LTC1598L provide a break-before-make
interval from switching off all the channels simulta-
neously to switching on the next selected channel once
CS is pulled low. In other words, once CS is pulled low,
Data Transfer
The CLK synchronizes the data transfer with each bit
being transmitted on the falling CLK edge and captured
on the rising CLK edge in both transmitting and receiving
systems.
The LTC1594L/LTC1598L first receive input data and
then transmit back the A/D conversion results (half
duplex). Because of the half duplex operation, D
IN
and
D
OUT
may be tied together allowing transmission over
just 3 wires: CS, CLK and DATA (D
IN
/D
OUT
).
Data transfer is initiated by a rising chip select (CS)
signal. After CS rises, the input data on the D
IN
pin is
latched into a 4-bit register on the rising edge of the clock.
More than four input bits can be sent to the D
IN
pin
without problems, but only the last four bits clocked in
before CS falls will be stored into the 4-bit register. This
4-bit input data word will select the channel in the
muliplexer (see Input Data Word and Tables 1 and 2). To
ensure correct operation, the CS must be pulled low
before the next rising edge of the clock.
Once the CS is pulled low, all channels are simulta-
neously switched off after a delay of t
OFF
to ensure a
