19
LTC1594L/LTC1598L
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specification in the Dynamic Accuracy table includes the
2nd through 5th harmonics. With a 1kHz input signal, the
LTC1594L/LTC1598L have typical THD of 78dB with
V
CC
= 2.7V.
Intermodulation Distortion
If the ADC input signal consists of more than one
spectral component, the ADC transfer function nonlin-
earity can produce intermodulation distortion (IMD)
in addition to THD. IMD is the change in one sinusoi-
dal input caused by the presence of another sinusoidal
input at a different frequency.
If two pure sine waves of frequencies f
a
and f
b
are applied
to the ADC input, nonlinearities in the ADC transfer
function can create distortion products at sum and differ-
ence frequencies of mf
a
± nf
b
, where m and n = 0, 1, 2, 3,
etc. For example, the 2nd order IMD terms include (f
a
+
f
b
) and (f
a
– f
b
) while 3rd order IMD terms include (2f
a
+
f
b
), (2f
a
– f
b
), (f
a
+ 2f
b
), and (f
a
– 2f
b
). If the two input sine
waves are equal in magnitudes, the value (in dB) of the
2nd order IMD products can be expressed by the follow-
ing formula:
APPLICATIONS INFORMATION
WUU
U
TYPICAL APPLICATIONS N
U
Microprocessor Interfaces
The LTC1594L/LTC1598L can interface directly (without
external hardware) to most popular microprocessors’
(MPU) synchronous serial formats including
MICROWIRE, SPI and QSPI. If an MPU without a dedi-
cated serial port is used, then three of the MPU’s parallel
port lines can be programmed to form the serial link to the
LTC1594L/LTC1598L. Included here is one serial interface
example.
Motorola SPI (MC68HC05)
The MC68HC05 has been chosen as an example of an MPU
with a dedicated serial port. This MPU transfers data MSB-
first and in 8-bit increments. The D
IN
word sent to the data
register starts the SPI process. With three
8-bit transfers the A/D result is read into the MPU. The
second 8-bit transfer clocks B11 through B7 of the A/D
conversion result into the processor. The third 8-bit trans-
fer clocks the remaining bits B6 through B0 into the MPU.
ANDing the second byte with 1F
HEX
clears the three most
significant bits and ANDing the third byte with FE
HEX
clears
the least significant bit. Shifting the data to the right by one
bit results in a right justified word.
IMD f f
mplitude f f
ab
ab
±
()
=
±
()
20log
a
amplitude at f
a
Peak Harmonic or Spurious Noise
The peak harmonic or spurious noise is the largest
spectral component excluding the input signal and DC.
This value is expressed in dBs relative to the RMS value
of a full-scale input signal.
Full-Power and Full-Linear Bandwidth
The full-power bandwidth is that input frequency at
which the amplitude of the reconstructed fundamental is
reduced by 3dB for a full-scale input.
The full-linear bandwidth is the input frequency at which
the effective bits rating of the ADC falls to 11 bits. Beyond
this frequency, distortion of the sampled input signal
increases. The LTC1594L/LTC1598L have been designed
to optimize input bandwidth, allowing the ADCs to
undersample input signals with frequencies above the
converters’ Nyquist Frequency.
20
LTC1594L/LTC1598L
15948lfb
TYPICAL APPLICATIONS N
U
LDA #$52 Configuration data for serial peripheral
control register (Interrupts disabled, output
enabled, master, Norm = 0, Ph = 0, Clk/16)
STA $0A Load configuration data into location $0A (SPCR)
LDA #$FF Configuration data for I/O ports
(all bits are set as outputs)
STA $04 Load configuration data into Port A DDR ($04)
STA $05 Load configuration data into Port B DDR ($05)
STA $06 Load configuration data into Port C DDR ($06)
LDA #$08 Put D
IN
word for LTC1598L into Accumulator
(CH0 with respect to GND)
STA $50 Load D
IN
word into memory location $50
START BSET 0,$02 Bit 0 Port C ($02) goes high (CS goes high)
LDA $50 Load D
IN
word at $50 into Accumulator
STA $0C Load D
IN
word into SPI data register ($0C) and
start clocking data
LOOP1 TST $0B Test status of SPIF bit in SPI status register ($0B)
MC68HC05 CODE
BPL LOOP1 Loop if not done with transfer to previous instruction
BCLR 0,$02 Bit 0 Port C ($02) goes low (CS goes low)
LDA $0C Load contents of SPI data register into Accumulator
STA $0C Start next SPI cycle
LOOP2 TST $0B Test status of SPIF
BPL LOOP2 Loop if not done
LDA $0C Load contents of SPI data register into Accumulator
STA $0C Start next SPI cycle
AND #$IF Clear 3 MSBs of first D
OUT
word
STA $00 Load Port A ($00) with MSBs
LOOP3 TST $0B Test status of SPIF
BPL LOOP3 Loop if not done
LDA $0C Load contents of SPI data register into Accumulator
AND #$FE Clear LSB of second D
OUT
word
STA $01 Load Port B ($01) with LSBs
JMP START Go back to start and repeat program
1594L/98L TA04
D
OUT
FROM LTC1598L STORED IN MC68HC05 RAM
B1 B0
0
B2
B3
B5
B6 B4
0
0
LSB
MSB
#00
#01
0
B11 B10
B9
B8 B7
CLK
D
IN
CSMUX
CSADC
ANALOG
INPUTS
C0
SCK
MC68HC05
D
OUT
MOSI
LTC1598L
BYTE 1
BYTE 2
MISO
Hardware and Software Interface to Motorola MC68HC05
Data Exchange Between LTC1598L and MC68HC05
CSMUX
= CSADC
= CS
CLK
D
OUT
MPU
RECEIVED
WORD
1594L/98L TA03
B3B7 B6 B5 B4 B2 B1 B0 B1 B2B11 B10 B9 B8
D
IN
MPU
TRANSMIT
WORD
BYTE 3
BYTE 2
EN D20D1
XD0
BYTE 1
X
X
X
X
X
X
X
000
X
X
X
XX
X
X
X
BYTE 3
BYTE 2
BYTE 1
B10
?
?
0
B11
B9
B7
B8
B6
B5
B3
B4 B2
B1
B1
B0
DON‘T CARE
D1D2
???
?????
DO
EN
21
LTC1594L/LTC1598L
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TYPICAL APPLICATIONS N
U
MULTICHANNEL A/D USES A SINGLE
ANTIALIASING FILTER
This circuit demonstrates how the LTC1598L’s indepen-
dent analog multiplexer can simplify design of a 12-bit
data acquisition system. All eight channels are MUXed into
a single 1kHz, 4th order Sallen-Key antialiasing filter,
which is designed for single supply operation. Since the
LTC1598L’s data converter accepts inputs from ground to
the positive supply, rail-to-rail op amps were chosen for
the filter to maximize dynamic range. The LT1368 dual rail-
to-rail op amp is designed to operate with 0.1µF load
capacitors (C1 and C2). These capacitors provide fre-
quency compensation for the amplifiers and help reduce
the amplifier’s output impedance and improve supply
rejection at high frequencies. The filter contributes less
than 1LSB of error due to offsets and bias currents. The
filter’s noise and distortion are less than –72dB for a
100Hz, 2V
P-P
offset sine input.
The combined MUX and A/D errors result in an integral
nonlinearity error of ±3LSB (maximum) and a differential
nonlinearity error of ±3/4LSB (maximum). The typical
signal-to-noise plus distortion ratio is 68dB, with approxi-
mately –78dB of total harmonic distortion. The LTC1598L
is programmed through a 4-wire serial interface that is
compatible with MICROWIRE, SPI and QSPI. Maximum
serial clock speed is 200kHz, which corresponds to a
10.5kHz sampling rate.
The complete circuit consumes approximately 600µA
from a single 3V supply.
Simple Data Acquisition System Takes Advantage of the LTC1598L’s
MUXOUT/ADCIN Pins to Filter Analog Signals Prior to A/D Conversion
1594L/98L TA05
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
20
21
22
23
24
1
2
3
+
8-CHANNEL
MUX
8 COM
GND
4, 9
10
6
5, 14
7
11
CSADC
CSMUX
CLK
D
IN
D
OUT
12
13
NC
NC
12-BIT
SAMPLING
ADC
SERIAL DATA LINK
MICROWIRE AND SPI
COMPATIBLE
ADCINMUXOUT
18
3
8
1
2
17 16
3.3V
3.3V
15, 19
C7
1µF
V
REF
V
CC
LTC1598L
C6
0.1µF
+
C2
0.015µF
C8
0.01µF
R2
7.5k
R3
7.5k
R4
7.5k
R1
7.5k
C4
0.03µF
C3
0.1µF
C5
0.015µF
C1
0.03µF
1/2 LT1368
5
7
6
4
+
1/2 LT1368

LTC1598LIG#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 12-Bit 8/Ch Low Pwr ADC 3V
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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