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AFCT-5964NLZ

P1-P3P4-P6P7-P9P10-P12P13-P15
7
Figure 6a. Recommended dc coupled interface circuit
Application Information
The Applications Engineering Group at Avago Technologies
is available to assist you with technical understanding and
design trade-o s associated with these transceivers. You
can contact them through your Avago Technologies sales
representative.
The following information is provided to answer some of
the most common questions about the use of the parts.
Optical Power Budget and Link Penalties
The worst-case Optical Power Budget (OPB) in dB for a
ber-optic link is determined by the di erence between
the minimum transmitter output optical power (dBm avg)
and the lowest receiver sensitivity (dBm avg). This OPB
provides the necessary optical signal range to establish a
working  ber-optic link. The OPB is allocated for the  ber-
optic cable length and the corresponding link penalties.
For proper link performance, all penalties that a ect the
link performance must be accounted for within the link
optical power budget.
Electrical and Mechanical Interface
Recommended Circuit
Figures 6a and 6b show recommended dc and ac coupled
circuits for deploying the Avago Technologies transceivers
in +3.3 V systems.
Data Line Interconnections
Avago Technologies’ AFCT-5964TLZ/TGZ/ATLZ/ATGZ/
NLZ/NGZ  ber-optic transceivers are designed to couple to
+3.3 V PECL signals. The transmitter driver circuit regulates
the output optical power. The regulated light output will
maintain a constant output optical power provided the
data pattern is reasonably balanced in duty cycle. If the
data duty cycle has long, continuous state times (low or
high data duty cycle), then the output optical power will
gradually change its average output optical power level
to its preset value.
Note: C1 = C2 = C3 = 10 nF or 100 nF
Note A: The bias resistor for VpdR should not exceed 200
* C4 and C5 are optional bypass capacitors for additional low frequency noise  ltering.
o VpdR
o V
EE
RX
o V
EE
RX
o DNC
o DNC
o V
EE
RX
o V
CC
RX
o SD
o RD-
o RD+
SD LVTTL
LV PECL
LV PECL
RD+
RD-
123 4567
P
MON
+o
P
MON
- o
B
MON
+o
B
MON
-o
V
EE
TX
o
TD- o
TD+ o
T
DIS
o
V
EE
TX o
V
CC
TX o
T
X
R
X
130 :
130 :
V
CC
RX (+ 3.3 V)
P
MON
+
P
MON
-
B
MON
+
B
MON
-
T
DIS
(LVT TL)
8910
20 19 18 17 16 15 14 13 12 11
TD-
TD+
200 :
NOTE A
10 nF
1 PH
1 PH
C2
C1
C3 10 PF
V
CC
(+ 3.3 V)
V
CC
(+ 3.3 V)
V
CC
(+ 3.3 V)
C4*
10 PF
C5*
10 PF
100 :
100 :
TERMINATE AT
TRANSCEIVER INPUTS
PHY DEVICE
TERMINATE AT
DEVICE INPUTS
130 : 130 :
Z = 50 :
Z = 50 :
Z = 50 :
Z = 50 :
Z = 50 :
8
The AFCT-5964TLZ/TGZ/ATLZ/ATGZ/NLZ/NGZ have a
transmit disable function which is a single-ended +3.3 V
TTL input which is dc-coupled to pin 13. In addition these
devices o er the designer the option of monitoring the
laser diode bias current and the laser diode optical power.
The voltage measured between pins 17 and 18 is propor-
tional to the bias current through an internal 10 resistor.
Similarly the optical power rear facet monitor circuit
provides a photo current which is proportional to the
voltage measured between pins 19 and 20, this voltage is
measured across an internal 200 resistor.
As for the receiver section, it is internally AC-coupled
between the preampli er and the postampli er stages.
The actual Data and Data-bar outputs of the postampli er
are DC-coupled to their respective output pins (pins 9,
10). The two data outputs of the receiver should be termi-
nated with identical load circuits.
Signal Detect is a single-ended, +3.3 V TTL output signal
that is DC-coupled to pin 8 of the module. Signal Detect
should not be AC-coupled externally to the follow-on
circuits because of its infrequent state changes.
The designer also has the option of monitoring the PIN
photo detector bias current. Figure 6b shows a resistor
network, which could be used to do this. Note that the
photo detector bias current pin must be connected to
V
CC
. Avago Technologies also recommends that a decou-
pling capacitor is used on this pin.
Power Supply Filtering and Ground Planes
It is important to exercise care in circuit board layout to
achieve optimum performance from these transceivers.
Figures 6a and 6b show the power supply circuit which
complies with the small form factor multisource agree-
ment. It is further recommended that a continuous ground
plane be provided in the circuit board directly under the
transceiver to provide a low inductance ground for signal
return current. This recommendation is in keeping with
good high frequency board layout practices.
Figure 6b. Recommended ac coupled interface circuit
Note: C1 = C2 = C3 = 10 nF or 100 nF
Note A: Circuit assumes open emitter output
Note B: When internal bias is provided replace split resistors with 100 termination
Note C: The bias resistor for VpdR should not exceed 200
* C4 and C5 are optional bypass capacitors for additional low frequency noise  ltering.
o
o
o
o
o
o
o
o
o
o
Z = 50 :
Z = 50 :
Z = 50 :
Z = 50 :
SD
LVTTL
V
CC
(+ 3.3 V)
V
CC
(+ 3.3 V)
RD+
RD-
Z = 50 :
1
o
o
o
o
o
o
o
o
o
o
130 :
130 :
130 :
130 :
100 nF
100 nF
100 nF
100 nF
82 :
130 :
V
CC
(+ 3.3 V)
130 :
82 :
23 45678910
20 19 18 17 16 15 14 13 12 11
TD-
TD+
10 nF
NOTE A
NOTE B
100 nF
1 PH
C2
1 PH
C1
C3
10 PF
V
CC
(+ 3.3 V)
C4*
10 PF
C5*
10 PF
100 nF
82 :
130
:
V
CC
(+ 3.3 V)
82 :
130
:
VpdR
V
EE
RX
V
EE
RX
DNC
DNC
V
EE
RX
V
CC
RX
SD
RD-
RD+
P
MON
+
P
MON
-
B
MON
+
B
MON
-
V
EE
TX
TD-
TD+
T
DIS
V
EE
TX
V
CC
TX
T
X
R
X
V
CC
RX (+ 3.3 V)
P
MON
+
P
MON
-
B
MON
+
B
MON
-
T
DIS
(LVT TL)
200 :
NOTE C
9
Figure 7. Recommended Board Layout Hole Pattern
Electromagnetic Interference (EMI)
One of a circuit board designer’s foremost concerns is
the control of electromagnetic emissions from electronic
equipment. Success in controlling generated Electro-
magnetic Interference (EMI) enables the designer to pass
a governmental agency’s EMI regulatory standard and
more importantly, it reduces the possibility of interfer-
ence to neighboring equipment. Avago Technologies has
designed the AFCT-5964TLZ/TGZ/ATLZ/ATGZ/NLZ/NGZ
to provide excellent EMI performance. The EMI perfor-
mance of a chassis is dependent on physical design and
features which help improve EMI suppression. Avago
Technologies encourages using standard RF suppression
practices and avoiding poorly EMI-sealed enclosures.
Avago Technologies OC-3 LC transceivers (AFCT-5964TLZ/
TGZ/ATLZ/ATGZ/NLZ/NGZ) have nose shields which
provide a convenient chassis connection to the nose of
the transceiver. This nose shield improves system EMI
performance by e ectively closing o the LC aperture.
The recommended transceiver position, PCB layout and
panel opening for these devices are the same, making
them mechanically drop-in compatible. Figure 8 shows
the recommended positioning of the transceivers with
respect to the PCB and faceplate.
Package footprint and front panel considerations
Avago Technologies transceivers comply with the circuit
board “Common Transceiver Footprint” hole pattern
de ned in the current multisource agreement which
de ned the 2 x 10 package style. This drawing is repro-
duced in Figure 7 with the addition of ANSI Y14.5M
compliant dimensioning to be used as a guide in the
mechanical layout of your circuit board. Figure 8 shows
the front panel dimensions associated with such a layout.
Eye Safety Circuit
For an optical transmitter device to be eye-safe in the
event of a single fault failure, the transmitter must either
maintain eye-safe operation or be disabled.
The AFCT-5964TLZ/TGZ/ATLZ/ATGZ/NLZ/NGZ is intrinsi-
cally eye safe and does not require shut down circuitry.
Signal Detect
The Signal Detect circuit provides a de-asserted output
signal when the optical link is broken (or when the
remote transmitter is OFF). The Signal Detect threshold
is set to transition from a high to low state between the
minimum receiver input optical power and -45 dBm avg.
input optical power indicating a de nite optical fault
(e.g. unplugged connector for the receiver or transmitter,
broken  ber, or failed far-end transmitter or data source).
The Signal Detect does not detect receiver data error or
error-rate. Data errors can be determined by signal pro-
cessing o ered by upstream PHY ICs.
Dimensions in millimeters (inches)
Notes:
1. This gure describes the recommended circuit
board layout for the SFF transceiver.
2. The hatched areas are keep-out areas reserved
for housing stando s. No metal traces or ground
connection in keep-out areas.
3. 2 X 10 transceiver module requires 26 PCB holes
(20 I/O pins, 2 solder posts and 4 optional pack-
age grounding tabs). Package grounding tabs
should be connected to signal ground.
*4. The mounting studs should be soldered to
chassis ground for mechanical integrity and to
ensure footprint compatibility with other SFF
transceivers.
*5. Holes for optional housing leads must be tied to
signal ground.
7.59
(0.299)
3
(0.118)
3
(0.118)
6
(0.236)
4.57
(0.18)
9 x 1.78
(0.07)
16
(0.63)
20 x Ø 0.81
±0.1
(0.032 ±0.004)
3.08
(0.121)
2 x Ø 2.29
(0.09)
9.59
(0.378)
2
(0.079)
13.34
(0.525)
7.11
(0.28)
4 x Ø 1.4 ±0.1
(0.055 ±0.004)
2 x Ø 1.4
±0.1
(0.055 ±0.004)
2 x Ø 1.4
±0.1
(0.055 ±0.004)
10.16
(0.4)
3.56
(0.14)
2 x Ø 2.29 MAX.
(0.09)
8.89
(0.35)
2
(0.079)
*4
*5
P1-P3P4-P6P7-P9P10-P12P13-P15

AFCT-5964NLZ

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Fiber Optic Transmitters, Receivers, Transceivers Transceive
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