IDT5T9306 REVISION C NOVEMBER 29, 2012 13 ©2012 Integrated Device Technology, Inc.
IDT5T9306 Data Sheet 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II
Figure 2 shows an example of IDT5T9306 schematic. In this
example, the device is operated at V
DD
= 2.5V. As with any high
speed analog circuitry, the power supply pins are vulnerable to
random noise. To achieve optimum jitter performance, power
supply isolation is required.
In order to achieve the best possible filtering, it is recommended
that the placement of the filter components be on the device side
of the PCB as close to the power pins as possible. If space is
limited, the 0.1μF capacitor in each power pin filter should be
placed on the device side of the PCB and the other components
can be placed on the opposite side.
Power supply filter recommendations are a general guideline to
be used for reducing external noise from coupling into the
SCHEMATIC LAYOUT
devices. The filter performance is designed for a wide range of
noise frequencies. This low-pass filter starts to attenuate noise
at approximately 10kHz. If a specific frequency noise component
is known, such as switching power supplies frequencies, it is
recommended that component values be adjusted and if
required, additional filtering be added. Additionally, good
general design practices for power plane voltage stability
suggests adding bulk capacitance in the local area of all devices.
The schematic example focuses on functional connections and
is not configuration specific. Refer to the pin description and
functional tables in the datasheet to ensure that the logic control
inputs are properly set.
Q1
VDD
VD D
Q1
A1
C6
0.1uF
Alternate
LVDS
Termi nat ion
LVDS Termination
Zo = 50
/Q1
RD1
Not Install
C4
0. 1 uF
R4
50
/Q 6
Q5
C7
0. 1 uF
/Q6
C8
0.1uF
Q3
Zo_Diff = 100 Ohm
/Q2
C9
0.1uF
VD D
/Q1
R6
50
RU1
1K
Q4
VD D
+
-
SEL
C10
10uF
R8
100
A2
Zo = 50
Q6
2. 5 V LV PE C L D r i v e r
/G
VDD
R7
50
Z o_D if f = 100 Ohm
U1
1
2
3
4
5
6
7
8
9
11
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
28
27
29
/G
VDD
Q1
/Q1
VDD
A1
/A1
GL
VD D
/Q 2
Q2
Q3
/Q 3
VDD
/A2
A2
VD D
/Q 4
Q4
VD D
/PD
NC
/Q 5
Q5
/Q 6
Q6
SEL
VD D
GND
Logic Input Pin Examples
To L ogic
In put
pi ns
VD D
BL M1 8B B2 21SN 1
Ferrite B ead
1 2
C3
0.1uF
LVDS Driv er
+
-
Q2
RD2
1K
C1
0.1uF
Q6
Zo_Di ff = 100 Ohm
/Q5/Q3
RU2
Not Install
VDD=2. 5V
VD D
To Logic
In put
pins
GL
C5
0.1uF
2.5V
C2
0. 1 uF
Set Logic
Input to
'1'
R2
18
/Q4
R1
100
VD D
/P D
/A2
VD D
Set Logic
Input to
'0'
/A1
R5
50
VDD
FIGURE 2. IDT5T3906 SCHEMATIC EXAMPLE
IDT5T9306 REVISION C NOVEMBER 29, 2012 14 ©2012 Integrated Device Technology, Inc.
IDT5T9306 Data Sheet 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II
RECOMMENDED LANDING PATTERN
NL 28 pin
NOTE: All dimensions are in millimeters.
IDT5T9306 REVISION C NOVEMBER 29, 2012 15 ©2012 Integrated Device Technology, Inc.
IDT5T9306 Data Sheet 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II
July 23, 2002 Datasheet creation
October 8, 2002 Page 1, entire page changed; page 2, both diagrams; page 3, Pin Description and notes; page 4, DC Cha. for LVPECL
and Differential Input tables; page 6, DC Cha. and Power Supply tables; page 7, entire page; page 9, added note 3; page
10, entire page; page 10, entire page; page 11, entire page; page 12, Ordering Info; added 3 new pages (10 thru 12) of
diagrams.
October 10, 2002 Page 1, entire page changed; page 2, both diagrams; page 3, Pin Description and notes; page 7, AC Cha. table; page
8, added new LVPECL table; page 10, removed Input Clock Switching diagram; page 11, deleted entire page; page
12, changed Power Down Timing; page 15, Ordering Info.
October 24, 2002 Page 2, added note 1 to TQFP TOP VIEW text; page3, aded note 4 to Pin Description; page 4, replaced "Compliant
devices must meet" with the text "This device meets" in four instances; page 5, Differential Input table, note 1, changed
1V to 732mV and replaced "Compliant devices must meet" with the text "This device meets"; page 6, DC Electrical table,
Vdif row, changed Min. value to 0.1, and under Differential Input table replaced "Compliant devices must meet" with
the text "This device meets" page 7, Power Supply table, replaced ((TBD)) with 800MHz, and under AC Electrical table,
replaced ((TBD)) with 500; page 8, completely altered AC DIfferential table; page 12, LVDS Output table, replaced
((TBD)) with 3.
November 1, 2002 Radical changes to entire document.
December 12, 2002 Radical changes to entire document, using 5T9316 as a base.
December 16, 2002 Throughout document, removed "Differential" from title; page 7, Power Supply table, changed Max values, changed
F
REFERENCE value; page 10, note 1, changed Gx to G.
May 8, 2003 Page 2, corrected pinout diagram.
August 7, 2003 Page 1, Features text, 3rd bullet, changed 2ns to 1.75ns, 4th bullet, changed 800MHz to 1GHz, and 7th bullet, added
CML, on Description, 3rd line, added CML to list; page 4, Pin Descr., note 1, added "Differential CML levels", for
Description of PD row, replaced 2nd sentence with "Both 'true' and 'complementary' output will pull to Vdd"; page 5,
DC... for Differential Inputs table, removed note 5 and changed Vcm Max. from 3.5 to Vdd; page 7, Power Supply table,
changed 800MHz to 1GHz; page 8, AC Differential table, changed Vix and Vcm Max specs from 3.5V to Vdd, removed
notes 4 and 5, and placed entire table on page 7, for AC Elect. table, added notes 5 and 6, changed ((TBD)) to 300ps,
tplh Type to 1.25ns, and Max from 2ns to 1.75ns, and changed fo Max from 800MHz to 1GHz.
October 2, 2003 Page 1, Features, 7th bullet, added "3.3V / 2,5V LVTTL" to front, Description, added to 1st paragraph "A single-ended
3.3V / 2.5V LVTTL input can also be used to translate to LVDS outputs."; page 4, Pin Description table, added large block
of text to 2nd row, added "Single-ended 3.3V and 2.5V LVTTL levels" to note 1; page 5, DC for LVTTL table, added Vref
row and note 3, for DC for LVDS table, changed Ios ratings from 5 Typ, 7.5 Max to 12 Typ, 24 Max, and changed Iosd
ratings from 5 Typ, 7.5 Max to 6 Typ, 12 Max; page 7, Power Supply table, changed Ipd from 3 to 5.
March 26, 2004 Page 2, changed pin 22 to NC; page 3, changed pin 25 to NC; page 4, added NC row to Pin Description.
June 22, 2004 Removed TQFP package.
October 26, 2004 Inserted a page before Ordering Info and added Landing Pattern.
October 27, 2004 Added note to Landing Pattern.
October 29, 2004 Changed landing pattern diagram.
March 9, 2005 Page 6, switched Iddq and Itot values.
October 23, 2007 Page 7, added Additive Phase Jitter, RMS specs to the AC Electrical Characterisitcs Table.
April 15, 2008 Page 7, added Rise/Fall Time spec. to the AC Electrical Characteristics Table.
January 31, 2011 Page 12, added VFQFPN Thermal Release Path application note.
Updated to header/footer to new format.
March 13, 2012 Page 13, added schematic layout.
Page 16, corrected ordering information table.
May 30, 2012 Page 1, Features Section - changed Low Skew spec to <40ps (max) from <25ps.
Page 7, AC Charastics Table - tsk(o) Max from 25ps to 40ps.
November 29, 2012 Page 16, Removed leaded parts from Ordering Information
REVISION HISTORY SHEET

5T9306NLGI

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer 2.5V LVDS 1:6 Clock Buffer
Lifecycle:
New from this manufacturer.
Delivery:
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