IDT5T9306 REVISION C NOVEMBER 29, 2012 7 ©2012 Integrated Device Technology, Inc.
IDT5T9306 Data Sheet 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II
AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
(1,5)
Symbol Parameter Min. Typ. Max Unit
Skew Parameters
tSK(O) Same Device Output Pin-to-Pin Skew
(2)
40 ps
tSK(P) Pulse Skew
(3)
——125 ps
t
SK(PP) Part-to-Part Skew
(4)
——300 ps
Propagation Delay
t
PLH Propagation Delay A, A Crosspoint to Qn, Qn Crosspoint 1.25 1.75 ns
tPHL
fO Frequency Range
(6)
—— 1 GHz
Output Gate Enable/Disable Delay
tPGE Output Gate Enable Crossing VTHI to Qn/Qn Crosspoint ——3.5 ns
t
PGD Output Gate Disable Crossing VTHI to Qn/Qn Crosspoint Driven to GL Designated Level ——3.5 ns
Power Down Timing
tPWRDN PD Crossing VTHI to Qn = VDD, Qn = VDD ——100 μS
t
PWRUP Output Gate Disable Crossing VTHI to Qn/Qn Driven to GL Designated Level ——100 μS
RMS Additive Phase Jitter
RMS Additive Phase Jitter @ 25MHz (12kHz – 10MHz Integration Range) 0.541 ps
t
JIT RMS Additive Phase Jitter @ 125MHz (12kHz – 20MHz Integration Range) 0.159 ps
RMS Additive Phase Jitter @ 156.25MHz (12kHz – 20MHz Integration Range) 0.185 ps
Output Rise/Fall Time
tR/tF Output Rise/Fall Time
(6)
, (20% - 80%) 125 600 ps
NOTES:
1. AC propagation measurements should not be taken within the first 100 cycles of startup.
2. Skew measured between crosspoints of all differential output pairs under identical input and output interfaces, transitions and load conditions on any one device.
3. Skew measured is the difference between propagation delay times tPHL and tPLH of any differential output pair under identical input and output interfaces, transitions and load conditions on
any one device.
4. Skew measured is the magnitude of the difference in propagation times between any single differential output pair of two devices, given identical transitions and load conditions at identical
VDD levels and temperature.
5. All parameters are tested with a 50% input duty cycle.
6. Guaranteed by design but not production tested.
IDT5T9306 REVISION C NOVEMBER 29, 2012 8 ©2012 Integrated Device Technology, Inc.
IDT5T9306 Data Sheet 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II
tPLH
tPHL
tSK(O)
tSK(O)
Qn - Qn
Qm - Qm
+ VDIF
VDIF = 0
- V
DIF
+ VDIF
VDIF = 0
- V
DIF
A[1:2] - A[1:2]
+ VDIF
VDIF = 0
- V
DIF
1/fo
DIFFERENTIAL AC TIMING WAVEFORMS
Output Propagation and Skew Waveforms
NOTES:
1. Pulse skew is calculated using the following expression:
tSK(P) = | tPHL - tPLH |
Note that the tPHL and tPLH shown above are not valid measurements for this calculation because they are not taken from the same pulse.
2. AC propagation measurements should not be taken within the first 100 cycles of startup.
IDT5T9306 REVISION C NOVEMBER 29, 2012 9 ©2012 Integrated Device Technology, Inc.
IDT5T9306 Data Sheet 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II
Power Down Timing
NOTES:
1. It is recommended that outputs be disabled before entering power-down mode. It is also recommended that the outputs remain disabled until the device completes power-up after asserting
PD.
2. The POWER DOWN TIMING diagram assumes that GL is HIGH.
3. It should be noted that during power-down mode, the outputs are both pulled to VDD. In the POWER DOWN TIMING diagram this is shown when Qn-Qn goes to VDIF = 0.
A1 - A1
G
V
THI
VIH
VIL
Qn - Qn
+VDIF
VDIF=0
-
V
DIF
+VDIF
VDIF=0
-V
DIF
+VDIF
VDIF=0
-V
DIF
PD
A2 - A2
VTHI
VIH
VIL
Differential Gate Disable/Enable Showing Runt Pulse Generation
NOTE:
1. As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user's responsibility to time the G signal to avoid this problem.
tPLH
GL
G
Qn - Qn
tPGD tPGE
VIH
VTHI
VIL
VIH
VTHI
VIL
+ VDIF
VDIF = 0
- V
DIF
A[1:2] - A[1:2]
+ VDIF
VDIF = 0
- VDIF

5T9306NLGI

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer 2.5V LVDS 1:6 Clock Buffer
Lifecycle:
New from this manufacturer.
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