ADCLK846
Rev. B | Page 11 of 16
FUNCTIONAL DESCRIPTION
The ADCLK846 clock input is distributed to all output channels.
Each channel bank is pin programmable for either LVDS or
CMOS levels. This allows the selection of multiple logic
configurations ranging from 6 LVDS to 12 CMOS outputs,
along with other combinations using both types of logic.
CLOCK INPUTS
The differential inputs of the ADCLK846 are internally self-
biased. The clock inputs have a resistor divider, which sets the
common-mode level for the inputs. The complementary inputs
are biased about 30 mV lower than the true input to avoid
oscillations if the input signal ceases. See Figure 20 for
the equivalent input circuit.
The inputs can be ac-coupled or dc-coupled. Table 8 displays
a guide for input logic compatibility. If a single-ended input is
desired, this can be accommodated by ac or dc coupling to one
side of the differential input. Bypass the other input to ground
by a capacitor.
Note that jitter performance degrades with low input slew rate,
as shown in Figure 11. See Figure 28 through Figure 32 for
different termination schemes.
9kΩ 9.5kΩ
9kΩ 8.5kΩ
S
CLK
CLK
GND
07226-023
Figure 20. ADCLK846 Input Stage
AC-COUPLED APPLICATIONS
When ac coupling is desired, the ADCLK846 offers two
options. The first option requires no external components
(excluding the dc blocking capacitor); it allows the user to
couple the reference signal onto the clock input pins (see
Figure 31).
The second option allows the use of the V
REF
pin to set the dc
bias level for the ADCLK846. The V
REF
pin can be connected
to CLK and
CLK
through resistors. This method allows lower
impedance termination of signals at the ADCLK846 (see
). Figure 32
The internal bias resistors are still in parallel with the external
biasing. However, the relatively high impedance of the internal
resistors allows the external termination to V
REF
to dominate.
This is also useful if it is not desirable to offset the inputs slightly
as previously mentioned using only the internal biasing.
Table 8. Input Logic Compatibility
Supply (V) Logic Common Mode (V) Output Swing (V) AC-Coupled DC-Coupled
3.3 CML 2.9 0.8 Yes Not allowed
2.5 CML 2.1 0.8 Yes Not allowed
1.8 CML 1.4 0.8 Yes
Yes
3.3 CMOS 1.65 3.3 Not allowed
Not allowed
2.5 CMOS 1.25 2.5 Not allowed
Not allowed
1.8 CMOS 0.9 1.8 Yes
Yes
1.5 HSTL 0.75 0.75 Yes
Yes
LVDS 1.25 0.4 Yes
Yes
3.3 LVPECL 2.0 0.8 Yes
Not allowed
2.5 LVPECL 1.2 0.8 Yes
Yes
1.8 LVPECL 0.5 0.8 Yes Yes
