ADCLK846
Rev. B | Page 15 of 16
*
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
EXCEPT FOR EXPOSED PAD DIMENSION
OUTLINE DIMENSIONS
1
24
6
7
13
19
18
12
*
2.45
2.30 SQ
2.15
0.60 MAX
0.50
0.40
0.30
0.30
0.23
0.18
2.50 REF
0.50
BSC
12° MAX
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
1.00
0.85
0.80
SEATING
PLANE
PIN 1
INDICATOR
TOP
VIEW
3.75
BSC SQ
4.00
BSC SQ
PIN 1
INDICATOR
0.60 MAX
COPLANARITY
0.08
0.20 REF
0.23 MIN
EXPOSED
PA D
(BOTTOMVIEW)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
080808-A
Figure 33. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
CP-24-2
Dimensions shown in millimeters
ORDERING GUIDE
Model
1
Temperature Range Package Description Package Option
ADCLK846BCPZ
−40°C to +85°C 24-Lead LFCSP_VQ CP-24-2
ADCLK846BCPZ-REEL7
−40°C to +85°C 24-Lead LFCSP_VQ CP-24-2
ADCLK846/PCBZ Evaluation Board
1
Z = RoHS Compliant Part.
ADCLK846
Rev. B | Page 16 of 16
NOTES
©2009–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07226-0-5/10(B)

ADCLK846BCPZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Clock Buffer 1.8V 6LVDS/12 CMOS Outputs Low Pwr
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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