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ISL8705AIBZ-T

P1-P3P4-P6P7-P9P10-P12
1
®
FN6381.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL8700A, ISL8701A, ISL8702A,
ISL8703A, ISL8704A, ISL8705A
Adjustable Quad Sequencer
The ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A,
ISL8705A family of ICs provide four delay adjustable
sequenced outputs while monitoring an input voltage all with
a minimum of external components.
High performance DSP, FPGA, µP and various sub-systems
require input power sequencing for proper functionality at
initial power up and the ISL870XA provides this function
while monitoring the distributed voltage for over and
undervoltage compliance.
These ICs operate over the +3.3V to +24V nominal voltage
range. All have a user adjustable time from UV and OV
voltage compliance to sequencing start via an external
capacitor when in auto start mode and adjustable time delay
to subsequent ENABLE output signal via external resistors.
Additionally, the ISL8702A, ISL8703A, ISL8704A and
ISL8705A provide I/O for sequencing on and off operation
(SEQ_EN) and for voltage window compliance reporting
(FAULT) over the +3.3V to +24V nominal voltage range.
Easily daisy chained for more than 4 sequenced signals.
Altogether, the ISL870XA provides these adjustable features
with a minimum of external BOM. See Figure 1 for typical
implementation.
Features
• Adjustable Delay to Subsequent Enable Signal
• Adjustable Delay to Sequence Auto Start
• Adjustable Distributed Voltage Monitoring
• Under and Overvoltage Adjustable Delay to Auto Start
Sequence
• I/O Options
ENABLE (ISL8700A, ISL8702A, ISL8704A) and
ENABLE# (ISL8701A, ISL8703A, ISL8705A)
SEQ_EN (ISL8702A, ISL8703A) and
SEQ_EN# (ISL8704A, ISL8705A)
• Voltage Compliance Fault Output
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Power Supply Sequencing
• System Timing Function
Pinout
ISL870XA
(14 LD SOIC)
TOP VIEW
Ordering Information
PART NUMBER
(Note 1)
PART
MARKING
TEMP.
RANGE (°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL8700AIBZ* ISL8700AIBZ -40 to +85 14 Ld SOIC M14.15
ISL8701AIBZ* ISL8701AIBZ -40 to +85 14 Ld SOIC M14.15
ISL8702AIBZ* ISL8702AIBZ -40 to +85 14 Ld SOIC M14.15
ISL8703AIBZ* ISL8703AIBZ -40 to +85 14 Ld SOIC M14.15
ISL8704AIBZ* ISL8704AIBZ -40 to +85 14 Ld SOIC M14.15
ISL8705AIBZ* ISL8705AIBZ -40 to +85 14 Ld SOIC M14.15
ISL870XAEVAL1 Evaluation Platform
*Add “-T” suffix for tape and reel.
NOTES:
1. Intersil Pb-free plus anneal products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
ENABLE_D
ENABLE_C
ENABLE_B
ENABLE_A
1
2
3
4
5
VIN
TD
TC
TB
6
7
8
9
14
TIME
SEQ_EN (NC on ISL8700A/01A)
FAULT (NC on ISL8700A/01A)
OV
UV
GND
13
12
11
10
ISL8701A, ISL8703A, ISL8705A PINS 1-4 ARE ENABLE# FUNCTION
ISL8704A, ISL8705A PIN 9 IS SEQ_EN# FUNCTION
ENABLE_A
UV
OV
GND TB TC TD TIME
VIN
FAULT *
SEQ_EN *
ENABLE_B
ENABLE_C
ENABLE_D
3.3-24V
DC/DC
EN
DC/DC
EN
DC/DC
EN
DC/DC
EN
Vo1
Vo2
Vo3
V04
FIGURE 1. ISL870XA IMPLEMENTATION
* SEQ_EN and FAULT are not available on ISL8700A and ISL8701A
Ru
Rm
Rl
Data Sheet October 12, 2006
2
FN6381.0
October 12, 2006
Absolute Maximum Ratings Thermal Information
V
IN
, ENABLE(#), FAULT . . . . . . . . . . . . . . . . . . . . . . . 27V, to -0.3V
TIME, TB, TC, TD, UV, OV . . . . . . . . . . . . . . . . . . . . . +6V, to -0.3V
SEQ_EN(#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
IN
+0.3V, to -0.3V
ENABLE, ENABLE # Output Current . . . . . . . . . . . . . . . . . . . 10mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage Range (Nominal). . . . . . . . . . . . . . . . . . 3.3V to 24V
Thermal Resistance (Typical, Note 2) θ
JA
(°C/W)
14 Ld SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Maximum Junction Temperature (Plastic Package) . . . . . . . +125°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C
(SOIC Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
2. θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications Nominal V
IN
= 3.3V to +24V, T
A
= T
J
= -40°C to+85°C, Unless Otherwise Specified.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
UV AND OV INPUTS
UV/OV Rising Threshold V
UVRvth
1.16 1.21 1.28 V
UV/OV Falling Threshold V
UVFvth
1.06 1.10 1.18 V
UV/OV Hysteresis V
UVhys
V
UVRvth
- V
UVFvth
-104-mV
UV/OV Input Current I
UV
-10-nA
TIME, ENABLE/ENABLE# OUTPUTS
TIME Pin Charging Current I
TIME
-2.6-μA
TIME Pin Threshold V
TIME_VTH
1.9 2.0 2.25 V
Time from V
IN
Valid to ENABLE_A t
VINSEQpd
SEQ_EN = high, C
TIME
= open - 30 - μs
t
VINSEQpd_10
SEQ_EN = high, C
TIME
= 10nF - 7.7 - ms
t
VINSEQpd500
SEQ_EN = high, C
TIME
= 500nF - 435 - ms
Time from V
IN
Invalid to Shutdown t
shutdown
UV or OV to simultaneous shutdown - - 1 μs
ENABLE Output Resistance R
EN
I
ENABLE
= 1mA - 100 -
Ω
ENABLE Output Low Vol I
ENABLE
= 1mA - 0.1 - V
ENABLE Pull-down Current I
pulld
ENABLE = 1V 10 15 - mA
Delay to Subsequent ENABLE Turn-on/off t
del_120
R
TX
= 120kΩ 155 195 240 ms
t
del_3
R
TX
= 3kΩ 3.5 4.7 6 ms
t
del_0
R
TX
= 0Ω -0.5-ms
SEQUENCE ENABLE AND FAULT I/O
V
IN
Valid to FAULT Low t
FLTL
15 30 50 μs
V
IN
Invalid to FAULT High t
FLTH
-0.5-μs
FAULT Pull-down Current FAULT = 1V 10 15 - mA
SEQ_EN Pull-up Voltage V
SEQ
SEQ_EN open - 2.4 - V
SEQ_EN Low Threshold Voltage Vil
SEQ_EN
--0.3V
SEQ_EN High Threshold Voltage Vih
SEQ_EN
1.2 - - V
Delay to ENABLE_A Deasserted t
SEQ_EN_ENA
SEQ_EN low to ENABLE_A low - 0.2 1 μs
BIAS
IC Supply Current I
VIN_3.3V
V
IN
= 3.3V - 191 - μA
I
VIN_12V
V
IN
= 12V - 246 400 μA
I
VIN_24V
V
IN
= 24V - 286 - μA
V
IN
Power On Reset V
IN_POR
V
IN
low to high - 2.3 2.8 V
ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A
3
FN6381.0
October 12, 2006
Pin Descriptions
PINS
PIN NAME FUNCTION DESCRIPTION8700A 8701A 8702A 8703A 8704A 8705A
NA 1 NA 1 NA 1 ENABLE#_D Active low open drain sequenced output. Sequenced on after ENABLE#_C and first output
to sequence off for the ISL8701A, ISL8703A, ISL8705A. Tracks V
IN
upon bias.
1 NA 1 NA 1 NA ENABLE_D Active high open drain sequenced output. Sequenced on after ENABLE_C and first output
to sequence off for the ISL8700A, ISL8702A, ISL8704A. Pulls low with V
IN
< 1V.
NA 2 NA 2 NA 2 ENABLE#_C Active low open drain sequenced output. Sequenced on after ENABLE#_B and sequenced
off after ENABLE#_D for the ISL8701A, ISL8703A, ISL8705A. Tracks V
IN
upon bias.
2 NA 2 NA 2 NA ENABLE_C Active high open drain sequenced output. Sequenced on after ENABLE_B and sequenced
off after ENABLE_D for the ISL8700A, ISL8702A, ISL8704A. Pulls low with V
IN
< 1V.
NA 3 NA 3 NA 3 ENABLE#_B Active low open drain sequenced output. Sequenced on after ENABLE#_A and sequenced
off after ENABLE#_C for the ISL8701A, ISL8703A, ISL8705A. Tracks V
IN
upon bias.
3 NA 3 NA 3 NA ENABLE_B Active high open drain sequenced output. Sequenced on after ENABLE_A and sequenced
off after ENABLE_C for the ISL8700A, ISL8702A, ISL8704A. Pulls low with V
IN
< 1V.
NA 4 NA 4 NA 4 ENABLE#_A Active low open drain sequenced output. Sequenced on after CTIME period and sequenced
off after ENABLE#_B for the ISL8701A, ISL8703A, ISL8705A. Tracks V
IN
upon bias.
4 NA 4 NA 4 NA ENABLE_A Active high open drain sequenced output. Sequenced on after CTIME period and
sequenced off after ENABLE_B for the ISL8700A, ISL8702A, ISL8704A. Pulls low with V
IN
< 1V.
5 5 5 5 5 5 OV The voltage on this pin must be under its 1.22V Vth or the four ENABLE outputs will be
immediately pulled down. Conversely the 4 ENABLE# outputs will be released to be pulled
high via external pull-ups.
6 6 6 6 6 6 UV The voltage on this pin must be over its 1.22V Vth or the four ENABLE outputs will be
immediately pulled down. Conversely the 4 ENABLE# outputs will be released to be pulled
high via external pull-ups.
777777 GNDIC ground.
NA NA 8 8 8 8 FAULT The V
IN
voltage when not within the desired UV to OV window will cause FAULT to be
released to be pulled high to a voltage equal to or less than V
IN
via an external resistor.
NA NA 9 9 NA NA SEQ_EN This pin provides a sequence on signal input with a high input. Internally pulled high to ~2.4V.
NA NA NA NA 9 9 SEQ_EN# This pin provides a sequence on signal input with a low input. Internally pulled high to ~2.4V.
10 10 10 10 10 10 TIME This pin provides a 2.6µA current output so that an adjustable V
IN
valid to sequencing on
and off start delay period is created with a capacitor to ground.
11 11 11 11 11 11 TB A resistor connected from this pin to ground determines the time delay from ENABLE_A
being active to ENABLE _B being active on turn-on and also going inactive on turn-off via
the SEQ_IN input.
12 12 12 12 12 12 TC A resistor connected from this pin to ground determines the time delay from ENABLE_B
being active to ENABLE _C being active on turn-on and also going inactive on turn-off via
the SEQ_IN input.
13 13 13 13 13 13 TD A resistor connected from this pin to ground determines the time delay from ENABLE_C
being active to ENABLE _D being active on turn-on and also going inactive on turn-off via
the SEQ_IN input.
14 14 14 14 14 14 V
IN
IC Bias Pin Nominally 3.3V to 24V
This pin requires a 1μF decoupling capacitor close to IC pin.
ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A
P1-P3P4-P6P7-P9P10-P12

ISL8705AIBZ-T

Mfr. #:
Buy ISL8705AIBZ-T
Manufacturer:
Renesas / Intersil
Description:
Supervisory Circuits ADJ QD SEQNCR 14N W/ANNEAL
Lifecycle:
New from this manufacturer.
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