5
FN6381.0
October 12, 2006
On the ISL8702A, ISL8703A, ISL8704A and ISL8705A,
enabling of on or off sequencing can also be signaled via the
SEQ_EN or SEQ_EN# input pin once voltage compliance is
met. Initially, the SEQ_EN pin should be held low and
released when sequence start is desired. The SEQ# is
internally pulled high and sequencing is enabled when it is
pulled low. The on sequence of the ENABLE outputs is as
previously described. The off sequence feature is only
available on the variants having the SEQ_EN or the
SEQ_EN# inputs, these being the ISL8702A, ISL8703A,
ISL8704A, ISL8705A. The sequence is D off, then C off, then
B off and finally A off. Once SEQ_EN (SEQ_EN#) is signaled
low (high), the TIME cap is charged to 2V once again. Once
this Vth is reached, ENABLE_D transitions to its reset state
and CTIM is discharged. A delay and subsequent sequence
off is then determined by TD resistor to ENABLE_C. Likewise,
a delay to ENABLE_B and then ENABLE_A turn-off is
determined by TC and TB resistor values respectively.
With the ISL8700A, ISL8701A a quasi down sequencing of the
ENABLE outputs can be achieved by loading the ENABLE pins
with various value capacitors to ground. When a simultaneous
output latch off is invoked, the caps will set the falling ramp of
the various ENABLE outputs thus adjusting the time to Vth for
various DC/DC convertors or other circuitry.
Regardless of IC variant, the FAULT signal is always valid at
operational voltages and can be used as justification for
SEQ_EN release or even controlled with an RC timer for
sequence on.
Programming the Under and Overvoltage Limits
When choosing resistors for the divider remember to keep the
current through the string bounded by power loss at the top end
and noise immunity at the bottom end. For most applications,
total divider resistance in the 10kΩ to1000kΩ range is
advisable with high precision resistors being used to reduce
monitoring error. Although for the ISL870XA, two dividers of two
resistors each can be employed to separately monitor the OV
and UV levels for the V
IN
voltage. We will discuss using a
single three resistor string for monitoring the V
IN
voltage,
referencing Figure 1. In the three resistor divider string with Ru
(upper), Rm (middle) and Rl (lower), the ratios of each in
combination to the other two is balanced to achieve the desired
UV and OV trip levels. Although this IC has a bias range of 3.3V
to 24V, it can monitor any voltage >1.22V.
The ratio of the desired overvoltage trip point to the internal
reference is equal to the ratio of the two upper resistors to the
lowest (gnd connected) resistor.
The ratio of the desired undervoltage trip point to the internal
reference voltage is equal to the ratio of the uppermost (voltage
connected) resistor to the lower two resistors.
These assumptions are true for both rising (turn-on) or falling
(shutdown) voltages.
The following is a practical example worked out. For detailed
equatons on how to perform this operation for a given supply
requirement please see the next section.
1. Determine if turn-on or shutdown limits are preferred. In this
example, we will determine the resistor values based on the
shutdown limits.
2. Establish lower and upper trip level: 12V ±10% or 13.2V
(OV) and 10.8V (UV)
3. Establish total resistor string value: 100kΩ, Ir = divider
current
4. (Rm+Rl) x Ir = 1.1V @ UV and Rl x Ir = 1.2V @ OV
5. Rm+Rl = 1.1V/Ir @ UV = Rm+Rl = 1.1V/(10.8V/100kΩ) =
10.370kΩ
6. Rl = 1.2V/Ir @ OV = Rl = 1.2V/(13.2V/100kΩ) = 9.242k
Ω
7. Rm = 10.370kΩ - 9.242kΩ = 1.128kΩ
8. Ru = 100kΩ - 10.370kΩ = 89.630kΩ
9. Choose standard value resistors that most closely
approximate these ideal values. Choosing a different total
divider resistance value may yield a more ideal ratio with
available resistor’s values.
In our example, with the closest standard values of
Ru = 90.9kΩ, Rm = 1.13kΩ and Rl = 9.31kΩ, the nominal UV
falling and OV rising will be at 10.9V and 13.3V respectively.
Programming the ENABLE Output Delays
The delay timing between the four sequenced ENABLE outputs
are programmed with four external passive components. The
delay from a valid V
IN
(ISL8700A and ISL8701A) to
ENABLE_A and SEQ_EN being valid (ISL8702A, ISL8703A,
ISL8704A, ISL8705A) to ENABLE_A is determined by the
value of the capacitor on the TIME pin to GND. The external
TIME pin capacitor is charged with a 2.6µA current source.
Once the voltage on TIME is charged up to the internal
reference voltage,
(V
TIME_VTH
) the ENABLE_A output is
released out of its reset state. The capacitor value for a desired
delay (±10%) to ENABLE_A once V
IN
and SEQ_EN where
applicable has been satisfied is determined by:
C
TIME
= t
VINSEQpd
/770kΩ
Once ENABLE_A reaches V
TIME_VTH
,
the TIME pin is pulled
low in preparation for a sequenced off signal via SEQ_EN. At
this time, the sequencing of the subsequent outputs is started.
ENABLE_B is released out of reset after a programmable time,
then ENABLE_C, then ENABLE _D, all with their own
programmed delay times.
The subsequent delay times are programmed with a single
external resistor for each ENABLE output providing maximum
flexibility to the designer through the choice of the resistor value
connected from TB, TC and TD pins to GND. The resistor
values determine the charge and discharge rate of an internal
capacitor comprising an RC time constant for an oscillator
whose output is fed into a counter generating the timing delay
to ENABLE output sequencing.
The R
TX
value for a given delay time is defined as:
R
TX
= t
del
/1667nF
ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A
