MR45V064BMAZAATL Datasheet MR45V064BMAZAATL | P1-P3

FEDR45V064B-01

Issue Date: Jan 08, 2016

MR45V064B

64k(8,192-Word × 8-Bit) FeRAM (Ferroelectric Random Access Memory) SPI

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GENERAL DESCRIPTION

The MR45V064B is a nonvolatile 8,192-word x 8-bit ferroelectric random access memory (FeRAM) developed

in the ferroelectric process and silicon-gate CMOS technology. The MR45V064B is accessed using Serial

Peripheral Interface.Unlike SRAMs, this device, whose cells are nonvolatile, eliminates battery backup required

to hold data. This device has no mechanisms of erasing and programming memory cells and blocks, such as

those used for various EEPROMs. Therefore, the write cycle time can be equal to the read cycle time and the

power consumption during a write can be reduced significantly.

The MR45V064B can be used in various applications, because the device is guaranteed for the write/read

tolerance of 10

cycles per bit and the rewrite count can be extended significantly.

FEATURES

• 8,192-word × 8-bit configuration (Serial Peripheral Interface : SPI)

• A single 1.8V to 3.6V （3.3 V typ） power supply

• Operating frequency: 40MHz

• Read/write tolerance 10

cycles/bit

• Data retention 10 years

• Guaranteed operating temperature range −40 to 85°C (Extended temperature version)

• Package options:

8-pin plastic SOP (P-SOP8-200-1.27-T2K)

FEDR45V064B-01

MR45V064B

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PIN CONFIGURATION

Note:

Signal names that end with # indicate that the signals are negative-true logic.

PIN DESCRIPTIONS

Pin Name

Description

CS#

Chip Select (input, negative logic)

Latches an address by low input, activates the FeRAM, and enables a read or write

operation.

WP#

Write Protect( input , negative logic )

Write Protect pin controls write-operation to the status-register(BP0,BP1). This pin should

be fixed low or high in write-operations.

HOLD#

HOLD( input , negative logic )

Hold pin is used when the serial-communication suspended without disable the chip

select. When HOLD# is low ,the serial-output is in High-Z status and

serial-input/serial-clock are “Don’t Care” . CS# should be low in hold operation.

SCK

Serial Clock

Serial Clock is the clock input pin for setting for serial data timing. Inputs are latched on

the rising edge and output occur on the falling edge.

Serial input

SI pins are serial input pins for Operation-code , addresses ,and data-inputs .

Serial output

SO pins are serial output pins.

, V

Power supply

Apply the specified voltage to V

. Connect V

to ground.

lastic SOP

CS#

WP#

VSS

VCC

HOLD#

SCK

1 8

2 7

3 6

4 5

MR45V064B

FEDR45V064B-01

MR45V064B

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SPIMODE

SPI mode0（CPOL=0, CPHA=0）

SPI mode3（CPOL=1, CPHA=1）

STATUS REGISTER

Name Function

WIP Fixed to 0.

WEL Write Enable Latch. This indicates internal WEL condition.

BP0,BP1 Block Protect: These bits can be changed protect area.

This is the software protect.

SRWD

Status Register Write Disable（ SRWD ） : SRWD controls the effect of the

hardware WP# pin. This device will be in hardware-protect by combination of

SRWD and WP#.

0 Fixed to 0.

SRWD 0 0 0 BP1 BP0 WEL WIP

b7 b0

Status Register Write Disable

Block Protect Bits

Write Enable Latch

Write In Progress (Always 0)

SI LSB MSB

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

MR45V064BMAZAATL

Mfr. #:

Buy MR45V064BMAZAATL

Manufacturer:

Description:

F-RAM FeRAM/64Kbit 8Kb x 8 8pin SOP40MHz

Lifecycle:

New from this manufacturer.

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MR45V064BMAZAATL