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MR45V064BMAZAATL
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P20
FEDR45V064B-01
MR45V064B
4/20
OPERATION-CODE
Operation codes are listed in the table below.If the de
vice receives invalid o
peration code,the de
vice will be
diselected.
Instruction
Description
Instruction
format
WREN
Write Enable
0000 01
10
WRDI Write
Disable
0000
0100
RDSR
Read S
tatus Register
0000 0101
WRSR
Write S
tatus Register
0000 0001
READ
Read from Memory
Array
0000 001
1
WRITE
Write to Memory
Array
0000 0010
FSTRD
Fast Read from Memory
Array
0000 101
1
RDID
Read device ID
1001 1
1
1
1
FEDR45V064B-01
MR45V064B
5/20
COMMANDS
WREN
(Write Enable)
It is necessary to set Write Enable Latch
(
WEL
)
bit before write-operation (W
RITE and WRSR).
WREN command sets WEL bit.
WRDI
(Write Disable)
WRDI command resets WEL b
it.
CS
#
SC
K
SI
WP
#
Fixed “H”
0 1 2 3 4 5 6 7
SO
High-Z
CS
#
SC
K
SI
WP
#
Fixed “H”
0 1 2 3 4 5 6 7
SO
High-Z
FEDR45V064B-01
MR45V064B
6/20
RDSR
(READ Status Register)
The RDSR com
mand allows
to read data of st
atus register.
WRSR
(WRITE Status Register
)
WRSR command allows to write data to statu
s register
(SRWD,BP0,BP1). It is necessary to set Write Enable
Latch
(
WEL
)
bit by
WREN comm
and before e
xecuting WRSR.
CS
#
SC
K
SI
WP
#
Fixed “H”
0
SO
High-Z
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SRWD
BP1 BP0
WEL
WIP
SRWD
000
765432
1
07
CS
#
SC
K
SI
0
SO
High-Z
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
BP0 X
X
76543
2
1
0
BP1
X
X
X
SRWD
Note:
WP#=Fix
”H”
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P20
MR45V064BMAZAATL
Mfr. #:
Buy MR45V064BMAZAATL
Manufacturer:
Description:
F-RAM FeRAM/64Kbit 8Kb x 8 8pin SOP40MHz
Lifecycle:
New from this manufacturer.
Delivery:
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MR45V064BMAZAATL