Philips Semiconductors Product data
P89C60X2/61X2
80C51 8-bit Flash microcontroller family
64KB Flash, 512B/1024B RAM
2003 Sep 11
43
Expanded Data RAM Addressing
The P89C60X2 has internal data memory that is mapped into four
separate segments: the lower 128 bytes of RAM, upper 128 bytes of
RAM, 128 bytes Special Function Register (SFR), and 256 bytes
expanded RAM (ERAM) (768 bytes for the P89C61X2).
The four segments are:
1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are
directly and indirectly addressable.
2. The Upper 128 bytes of RAM (addresses 80H to FFH) are
indirectly addressable only.
3. The Special Function Registers, SFRs, (addresses 80H to FFH)
are directly addressable only.
4. The 256/768-bytes expanded RAM (ERAM, 00H – 1FFH/2FFH)
are indirectly accessed by move external instruction, MOVX, and
with the EXTRAM bit cleared, see Figure 29.
The Lower 128 bytes can be accessed by either direct or indirect
addressing. The Upper 128 bytes can be accessed by indirect
addressing only. The Upper 128 bytes occupy the same address
space as the SFR. That means they have the same address, but are
physically separate from SFR space.
When an instruction accesses an internal location above address
7FH, the CPU knows whether the access is to the upper 128 bytes
of data RAM or to SFR space by the addressing mode used in the
instruction. Instructions that use direct addressing access SFR
space. For example:
MOV 0A0H,#data
accesses the SFR at location 0A0H (which is P2). Instructions that
use indirect addressing access the Upper 128 bytes of data RAM.
For example:
MOV @R0,acc
where R0 contains 0A0H, accesses the data byte at address 0A0H,
rather than P2 (whose address is 0A0H).
The ERAM can be accessed by indirect addressing, with EXTRAM
bit cleared and MOVX instructions. This part of memory is physically
located on-chip, logically occupies the first 256/768 bytes of external
data memory in the P89C60X2/61X2.
With EXTRAM = 0, the ERAM is indirectly addressed, using the
MOVX instruction in combination with any of the registers R0, R1 of
the selected bank or DPTR. An access to ERAM will not affect ports
P0, P3.6 (WR#) and P3.7 (RD#). P2 SFR is output during external
addressing. For example, with EXTRAM = 0,
MOVX @R0,acc
where R0 contains 0A0H, accesses the ERAM at address 0A0H
rather than external memory. An access to external data memory
locations higher than the ERAM will be performed with the MOVX
DPTR instructions in the same way as in the standard 80C51, so
with P0 and P2 as data/address bus, and P3.6 and P3.7 as write
and read timing signals. Refer to Figure 30.
With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar
to the standard 80C51. MOVX @ Ri will provide an 8-bit address
multiplexed with data on Port 0 and any output port pins can be
used to output higher order address bits. This is to provide the
external paging capability. MOVX @DPTR will generate a 16-bit
address. Port 2 outputs the high-order eight address bits (the
contents of DPH) while Port 0 multiplexes the low-order eight
address bits (DPL) with data. MOVX @Ri and MOVX @DPTR will
generate either read or write signals on P3.6 (WR
) and P3.7 (RD).
The stack pointer (SP) may be located anywhere in the 256 bytes
RAM (lower and upper RAM) internal data memory. The stack may
not be located in the ERAM.
AUXR
Reset Value = xxxx xx00B
—————EXTRAM AO
Not Bit Addressable
Bit:
Symbol Function
AO Disable/Enable ALE
AO Operating Mode
0 ALE is emitted at a constant rate of
1
/
6
the oscillator frequency (12-clock mode;
1
/
3
f
OSC
in 6-clock mode).
1 ALE is active only during off-chip memory access.
EXTRAM Internal/External RAM access using MOVX @Ri/@DPTR
EXTRAM Operating Mode
0 Internal ERAM access using MOVX @Ri/@DPTR
1 External data memory access.
Not implemented, reserved for future use*.
NOTE:
*User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value
of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
SU01613
76543210
Address = 8EH
Figure 29. AUXR: Auxiliary Register
Philips Semiconductors Product data
P89C60X2/61X2
80C51 8-bit Flash microcontroller family
64KB Flash, 512B/1024B RAM
2003 Sep 11
44
ERAM
256 or 768 BYTES
UPPER
128 BYTES
INTERNAL RAM
LOWER
128 BYTES
INTERNAL RAM
SPECIAL
FUNCTION
REGISTER
100
FF
00
FF
00
80 80
EXTERNAL
DATA
MEMORY
FFFF
0000
SU01293
Figure 30. Internal and External Data Memory Address Space with EXTRAM = 0
HARDWARE WATCHDOG TIMER (ONE-TIME
ENABLED WITH RESET-OUT FOR
P89C51RA2/RB2/RC2/RD2xx)
The WDT is intended as a recovery method in situations where the
CPU may be subjected to software upset. The WDT consists of a
14-bit counter and the Watchdog Timer reset (WDTRST) SFR. The
WDT is disabled at reset. To enable the WDT, the user must write
01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H.
When the WDT is enabled, it will increment every machine cycle
while the oscillator is running and there is no way to disable the
WDT except through reset (either hardware reset or WDT overflow
reset). When the WDT overflows, it will drive an output reset HIGH
pulse at the RST-pin (see the note below).
Using the WDT
To enable the WDT, the user must write 01EH and 0E1H in
sequence to the WDTRST, SFR location 0A6H. When the WDT is
enabled, the user needs to service it by writing 01EH and 0E1H to
WDTRST to avoid a WDT overflow. The 14-bit counter overflows
when it reaches 16383 (3FFFH) and this will reset the device. When
the WDT is enabled, it will increment every machine cycle while the
oscillator is running. This means the user must reset the WDT at
least every 16383 machine cycles. To reset the WDT, the user must
write 01EH and 0E1h to WDTRST. WDTRST is a write only register.
the WDT counter cannot be read or written. When the WDT
overflows, it will generate an output RESET pulse at the reset pin
(see note below). The RESET pulse duration is 98 T
OSC
(6-clock
mode; 196 in 12-clock mode), where T
OSC
= 1/f
OSC
. To make the
best use of the WDT, it should be serviced in those sections of code
that will periodically be executed within the time required to prevent
a WDT reset.
Philips Semiconductors Product data
P89C60X2/61X2
80C51 8-bit Flash microcontroller family
64KB Flash, 512B/1024B RAM
2003 Sep 11
45
ABSOLUTE MAXIMUM RATINGS
1,
2,
3
PARAMETER
RATING UNIT
Operating temperature under bias 0 to +70 °C
Storage temperature range –65 to +150 °C
Voltage on EA/V
PP
pin to V
SS
0 to +13.0 V
Voltage on any other pin to V
SS
–0.5 to +6.5 V
Maximum I
OL
per I/O pin 15 mA
Power dissipation (based on package heat transfer limitations, not device power consumption) 1.5 W
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.
3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V
SS
unless otherwise
noted.
AC ELECTRICAL CHARACTERISTICS
T
amb
= 0°C to +70°C
CLOCK FREQUENCY
RANGE
SYMBOL FIGURE PARAMETER OPERATING MODE POWER SUPPLY
VOLTAGE
MIN MAX UNIT
1/t
CLCL
35 Oscillator frequency
6-clock 5 V " 10% 0 20 MHz
12-clock 5 V " 10% 0 33 MHz

P89C60X2BA/00,512

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC MCU 8BIT 64KB FLASH 44PLCC
Lifecycle:
New from this manufacturer.
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