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ADG728BRUZ

P1-P3P4-P6P7-P9P10-P12P13-P13
–10–
ADG728/ADG729
WRITE OPERATION
When writing to the ADG728/ADG729, the user must begin
with an address byte and R/W bit, after which the switch will
acknowledge that it is prepared to receive data by pulling SDA
low. This address byte is followed by the 8-bit word. The write
operations for each matrix switch are shown in the figures below.
SCL
SDA S8 S7 S6 S5 S4 S3 S2 S100 1 1 A0R/W
STOP
COND
BY
MASTER
ACK
BY
ADG728
START
COND
BY
MASTER
ADDRESS BYTE
DATA BYTE
ACK
BY
ADG728
A1
1
Figure 16. ADG728 Write Sequence
SCL
SDA S8 S7 S6 S5 S4 S3 S2 S100 1 A0R/W
STOP
COND
BY
MASTER
ACK
BY
ADG729
START
COND
BY
MASTER
ADDRESS BYTE
DATA BYTE
ACK
BY
ADG729
A1
1
0
Figure 17. ADG729 Write Sequence
READ OPERATION
When reading data back from the ADG728/ADG729, the user must begin with an address byte and R/W bit, after which the ma-
trix switch will acknowledge that it is prepared to transmit data by pulling SDA low. The readback operation is a single byte that
consists of the eight data bits in the input register. The read operations for each part are shown in Figures 18 and 19.
SCL
SDA S8 S7 S6 S5 S4 S3 S2 S100 1 A0R/W
STOP
COND
BY
MASTER
ACK
BY
ADG728
START
COND
BY
MASTER
ADDRESS BYTE
DATA BYTE
NO ACK
BY
MASTER
A1
1
1
Figure 18. ADG728 Readback Sequence
SCL
SDA S8 S7 S6 S5 S4 S3 S2 S100 1 A0R/W
STOP
COND
BY
MASTER
ACK
BY
ADG729
START
COND
BY
MASTER
ADDRESS BYTE
DATA BYTE
NO ACK
BY
MASTER
A1
1
0
Figure 19. ADG729 Readback Sequence
REV. C
ADG728/ADG729
–11–
TEST CIRCUITS
I
DS
S
V
S
D
V
1
R
ON
= V
1
/I
DS
Test Circuit 1. On Resistance
I
S
(OFF)
S1
S2
S8
D
A
GND
V
DD
V
DD
V
D
V
S
Test Circuit 2. I
D
(OFF)
S1
S2
S8
D
GND
V
DD
V
DD
V
S
A
I
D
(OFF)
V
D
Test Circuit 3. I
S
(OFF)
S1
S8
D
GND
V
DD
V
DD
V
S
A
I
D
(ON)
V
D
Test Circuit 4. I
D
(ON)
GND
V
DD
V
DD
50%
t
OFF
90%
90%
50%
V
S1
80%
80%
V
S1
= V
S8
V
OUT
V
OUT
t
ON
t
OPEN
SCL
V
OUT
D
V
S1
ADG728*
S1
S8
S2 THRU S7
R
L
300⍀
C
L
35pF
V
S8
* SIMILAR CONNECTION FOR ADG729
Test Circuit 5. Switching Times and Break-Before-Make Times
MULTIPLE DEVICES ON ONE BUS
Figure 20 shows four ADG728s devices on the same serial bus.
Each has a different slave address since the state of their A0 and
A1 pins is different. This allows each Matrix Switch to be writ-
ten to or read from independently. Because the ADG729 has a
different address to the ADG728, it would be possible for four
of each of these devices to be connected to the same bus.
ADG728
A1
A0
SDA SCL
ADG728
A1
A0
SDA SCL
ADG728
A1
A0
SDA SCL
ADG728
A1
A0
SDA SCL
SCL
SDA
+5V
V
DD
MASTER
R
P
R
P
V
DD
V
DD
Figure 20. Multiple ADG728s on the Same Bus
ADG728/ADG729
–12–
SDA
V
DD
ADG728*
1nF
INPUT LOGIC
SWITCH OFF
SWITCH ON
V
OUT
C
L
V
S
R
S
⌬V
OUT
Q
INJ
= C
L
x ⌬V
OUT
D
* SIMILAR CONNECTION FOR ADG729
S
V
DD
SCL
GND
Test Circuit 6. Charge Injection
GND
ADG728*
50⍀
S1
S2
S8
* SIMILAR CONNECTION FOR ADG729
CHANNEL-TO-CHANNEL CROSSTALK = 20LOG
10
(V
OUT
/V
S
)
V
OUT
V
DD
R
L
V
DD
50⍀
V
S
D
Test Circuit 7. Channel-to-Channel Crosstalk
GND
ADG728*
50⍀
S1
S8
V
OUT
V
DD
R
L
V
DD
V
S
D
*SIMILAR CONNECTION FOR ADG729
OFF ISOLATION = 20LOG
10
(V
OUT
/V
S
)
V
OUT
WITHOUT SWITCH
INSERTION LOSS = 20LOG
10
V
OUT
WITH SWITCH
S1 IS SWITCHED OFF FOR OFF ISOLATION MEASURE-
MENTS AND ON FOR BANDWIDTH MEASUREMENTS
Test Circuit 8. Off Isolation and Bandwidth
REV. C
P1-P3P4-P6P7-P9P10-P12P13-P13

ADG728BRUZ

Mfr. #:
Buy ADG728BRUZ
Manufacturer:
Analog Devices Inc.
Description:
Multiplexer Switch ICs 8:1 65MHz 2.5 Ohm CMOS Serial Cntrld
Lifecycle:
New from this manufacturer.
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