ADG728/ADG729
–4– REV. C
TIMING CHARACTERISTICS
V
DD
= 2.7 V to 5.5 V. All specifications −40°C to +85°C, unless otherwise noted. See Figure 1.
Parameter Limit at T
MIN
, T
MAX
Unit Test Conditions/Comments
f
SCL
400 kHz max SCL clock frequency
t
1
2.5 µs min SCL cycle time
t
2
0.6 µs min SCL high time, t
HIGH
t
3
1.3
µs min
SCL low time, t
LOW
t
4
0.6
µs min
Start/repeated start condition hold time, t
HD, STA
t
5
100 ns min Data setup time, t
SU, DAT
t
6
1
0.9 µs max Data hold time, t
HD, D AT
0 µs min
t
7
0.6 µs min Setup time for repeated start, t
SU, STA
t
8
0.6 µs min Stop condition setup time, t
SU, STO
t
9
1.3 µs min Bus free time between a stop condition and a start condition, t
BUF
t
10
300 ns max Rise time of both SCL and SDA when receiving, t
R
20 + 0.1C
b
2
ns min
t
11
250 ns max Fall time of SDA when receiving, t
F
300 ns max Fall time of SDA when transmitting, t
F
0.1C
b
2
ns min
C
b
2
400 pF max Capacitive load for each bus line
t
SP
3
50 ns max Pulse width of spike suppressed
1
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V
IH
min of the SCL signal) to bridge the undefined region of the falling
edge of SCL.
2
C
b
is the total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3 V
DD
and 0.7 V
DD
.
3
Input filtering on both the SCL and SDA inputs suppress noise spikes that are less than 50 ns.
t
3
t
2
t
1
t
4
t
8
t
6
t
5
t
9
t
7
t
4
t
11
t
10
SDA
SCL
START
CONDITION
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITION
01002-002
Figure 1. 2-Wire Serial Interface Timing Diagram
ADG728/ADG729
–5–
PIN FUNCTION DESCRIPTIONS
ADG728 ADG729 Mnemonic Function
1 1 SCL Serial Clock Line. This is used in conjunction with the SDA line to clock data into
the 8-bit input shift register. Clock rates of up to 400 kbit/s can be accommodated
with this 2-wire serial interface.
2 RESET Active low control input that clears the input register and turns all switches to the
OFF condition.
3 3 SDA Serial Data Line. This is used in conjunction with the SCL line to clock data into
the 8-bit input shift register during the write cycle and used to read back 1 byte of
data during the read cycle. It is a bidirectional open-drain data line which should be
pulled to the supply with an external pull-up resistor.
4, 5, 6, 7 4, 5, 6, 7 Sxx Source. May be an input or output.
8 8, 9 Dx Drain. May be an input or output.
9, 10, 11, 12 10, 11, 12, 13
Sxx Source. May be an input or output.
13 14 V
DD
Power Supply Input. These parts can be operated from a supply of 2.7 V to 5.5 V.
14 15 GND Ground Reference.
15 2 A1 Address Input. Sets the second least significant bit of the 7-bit slave address.
16 16 A0 Address Input. Sets the least significant bit of the 7-bit slave address.
ADG729
SCL
S2A
S3A
S4A
S1A
DA
1
2
16
15
5
6
7
12
11
10
3
4
14
13
8
9
TOP VIEW
(Not to Scale)
A1 GND
V
DD
SDA
ADG729
A0
S2B
S3B
S4B
S1B
DB
ADG728
SCL
RESET
S2
S3
S4
S1
D
1
2
16
15
5
6
7
12
11
10
3
4
14
13
8
9
TOP VIEW
(Not to Scale)
A1
S5
S6
S7
GND
V
DD
S8
SDA
ADG728
A0
PIN CONFIGURATIONS
6
ADG728/ADG729
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= 25°C unless otherwise noted.)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog, Digital Inputs
2
. . . . . . . . . . –0.3 V to V
DD
+ 0.3 V or
30 mA, Whichever Occurs First
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
(Pulsed at 1 ms, 10% Duty Cycle max)
Continuous Current, Each S . . . . . . . . . . . . . . . . . . . . . 30 mA
Continuous Current D, ADG729 . . . . . . . . . . . . . . . . . 80 mA
Continuous Current D, ADG728 . . . . . . . . . . . . . . . . 120 mA
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG728/ADG729 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
TSSOP Package
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . 150.4°C/W
θ
JC
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 27.6°C/W
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2
Overvoltages at IN, S or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
TERMINOLOGY
C
D
, C
S
(ON) “ON” Switch Capacitance. Measured with refer-
ence to ground.
C
IN
Digital Input Capacitance.
t
ON
Delay time between the 50% and 90% points
of the STOP condition and the switch “ON”
condition.
t
OFF
Delay time between the 50% and 90% points
of the STOP condition and the switch “OFF”
condition.
t
D
“OFF” time measured between the 80% points of
both switches when switching from one switch to
another.
Charge A measure of the glitch impulse transferred from
Injection the digital input to the analog output during
switching.
Off Isolation A measure of unwanted signal coupling through
an “OFF” switch.
Crosstalk A measure of unwanted signal which is coupled
through from one channel to another as a result
of parasitic capacitance.
Bandwidth The frequency at which the output is attenuated
by 3 dBs.
On Response The frequency response of the “ON” switch.
Insertion The loss due to the ON resistance of the switch.
Loss
WARNING!
ESD SENSITIVE DEVICE
V
DD
Most Positive Power Supply Potential.
I
DD
Positive Supply Current.
GND Ground (0 V) Reference.
S Source Terminal. May be an input or output.
D Drain Terminal. May be an input or output.
V
D
(V
S
) Analog Voltage on Terminals D, S.
R
ON
Ohmic Resistance between D and S.
R
ON
On Resistance Match Between any Two Chan-
nels, i.e., R
ON
max – R
ON
min.
R
FLAT(ON)
Flatness is defined as the difference between the
maximum and minimum value of on resistance
as measured over the specified analog signal range.
I
S
(OFF) Source Leakage Current with the Switch “OFF.”
I
D
(OFF) Drain Leakage Current with the Switch “OFF.”
I
D
, I
S
(ON) Channel Leakage Current with the Switch “ON.”
V
INL
Maximum Input Voltage for Logic “0.”
V
INH
Minimum Input Voltage for Logic “1.”
I
INL
(I
INH
) Input Current of the Digital Input.
C
S
(OFF) “OFF” Switch Source Capacitance. Measured
with reference to ground.
C
D
(OFF) “OFF” Switch Drain Capacitance. Measured
with reference to ground.
REV. C
Lead Temperature, Soldering . . . . .
As per JEDEC J-STD-020

ADG728BRUZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Multiplexer Switch ICs 8:1 65MHz 2.5 Ohm CMOS Serial Cntrld
Lifecycle:
New from this manufacturer.
Delivery:
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