AD8007/AD8008
Rev. E | Page 16 of 20
Whenever physical layout considerations prevent the decoupling
scheme shown in Figure 53, the user can connect one of the
high frequency decoupling capacitors directly across the supplies
and connect the other high frequency decoupling capacitor to
ground (see Figure 54).
+V
S
–V
S
R
G
499
R
S
200
IN
R
F
499
OUT
AD8007
+
+
10µF
10µF
C1
0.1µF
C2
0.1µF
02866-054
Figure 54. High Frequency Capacitors Connected Across the Supplies
(Recommended)
LAYOUT CONSIDERATIONS
The standard noninverting configuration with recommended
power supply bypassing is shown in Figure 54. The 0.1 μF high
frequency decoupling capacitors should be X7R or NPO chip
components. Connect C2 from the +V
S
pin to the −V
S
pin.
Connect C1 from the +V
S
pin to signal ground.
The length of the high frequency bypass capacitor leads is critical.
Parasitic inductance due to long leads works against the low
impedance created by the bypass capacitor. The ground for the
load impedance should be at the same physical location as the
bypass capacitor grounds. For larger value capacitors, which are
intended to be effective at lower frequencies, the current return
path distance is less critical.
AD8007/AD8008
Rev. E | Page 17 of 20
LAYOUT AND GROUNDING CONSIDERATIONS
GROUNDING
A ground plane layer is important in densely packed printed
circuit boards (PCB) to minimize parasitic inductances. However,
an understanding of where the current flows in a circuit is critical
to implementing effective high speed circuit design. The length
of the current path is directly proportional to the magnitude of
parasitic inductances and thus the high frequency impedance of
the path. High speed currents in an inductive ground return
create unwanted voltage noise. Broad ground plane areas reduce
parasitic inductance.
INPUT CAPACITANCE
Along with bypassing and ground, high speed amplifiers can be
sensitive to parasitic capacitance between the inputs and ground.
Even 1 pF or 2 pF of capacitance reduces the input impedance at
high frequencies, in turn increasing the gain of the amplifier, which
causes peaking of the frequency response or even oscillations if
severe enough. Place the external passive components that are
connected to the input pins as close as possible to the inputs to
avoid parasitic capacitance. The ground and power planes must
be kept at a distance of at least 0.05 mm from the input pins on
all layers of the board.
OUTPUT CAPACITANCE
To a lesser extent, parasitic capacitances on the output can cause
peaking of the frequency response. The following two methods
minimize its effect:
Put a small value resistor in series with the output to isolate
the load capacitance from the output stage of the amplifier
(see Figure 12).
Increase the phase margin by increasing the gain of the
amplifier or by increasing the value of the feedback resistor.
INPUT-TO-OUTPUT COUPLING
To minimize capacitive coupling, the input and output signal
traces should not be parallel. When they are not parallel, they
help reduce unwanted positive feedback.
EXTERNAL COMPONENTS AND STABILITY
The AD8007/AD8008 are current feedback amplifiers and, to a
first order, the feedback resistor determines the bandwidth and
stability. The gain, load impedance, supply voltage, and input
impedances also have an effect.
Figure 11 shows the effect of changing R
F
on the bandwidth and
peaking for a gain of 2. Increasing R
F
reduces peaking but also
reduces bandwidth. Figure 6 shows that for a given R
F
increasing
the gain also reduces peaking and bandwidth. Table 4 shows the
recommended R
F
and R
G
values that optimize bandwidth with
minimal peaking.
Table 4. Recommended Component Values
Gain R
F
(Ω) R
G
(Ω) R
S
(Ω)
−1 499 499 200
+1 499 Not applicable 200
+2 499 499 200
+5 499 124 200
+10 499 54.9 200
The load resistor also affects bandwidth, as shown in Figure 7 and
Figure 10. A comparison between Figure 7 and Figure 10 also
demonstrates the effect of gain and supply voltage.
When driving loads with a capacitive component, stability
improves by using a series snub resistor, R
SNUB
, at the output.
The frequency and pulse responses for various capacitive
loads are illustrated in Figure 12 and Figure 47, respectively.
For noninverting configurations, a resistor in series with the
input, R
S
, is needed to optimize stability for a gain of 1, as
illustrated in Figure 8. For larger noninverting gains, the effect
of a series resistor is reduced.
AD8007/AD8008
Rev. E | Page 18 of 20
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-A A
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099)
45°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 55. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
COMPLIANT TO JEDEC STANDARDS MO-187-AA
091709-A
0.70
0.55
0.40
4
8
1
5
0.65 BSC
0.40
0.25
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.13
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
Figure 56. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters

AD8008ARMZ-REEL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
High Speed Operational Amplifiers Ultra Low Distortion
Lifecycle:
New from this manufacturer.
Delivery:
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