85322 Data Sheet
©2016 Integrated Device Technology, Inc Revision D January 20, 20164
TABLE 3D. POWER SUPPLY DC CHARACTERISTICS, V
CC
= 2.5V±5%, TA = 0°C TO 70°C
TABLE 3E. LVCMOS / LVTTL DC CHARACTERISTICS, V
CC
= 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage CLK0, CLK1 1.6 2.925 V
V
IL
Input Low Voltage CLK0, CLK1 -0.3 0.9 V
I
IH
Input High Current CLK0, CLK1 V
CC
= V
IN
= 2.625 5 µA
I
IL
Input Low Current CLK0, CLK1 V
CC
= V
IN
= 2.625 -150 µA
TABLE 3F. LVPECL DC CHARACTERISTICS, V
CC
= 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
OH
Output High Voltage; NOTE 1 V
CC
- 1.4 V
CC
- 0.9 V
V
OL
Output Low Voltage; NOTE 1 V
CC
- 2.0 V
CC
- 1.7 V
V
SWING
Peak-to-Peak Output Voltage Swing 0.65 1.0 V
NOTE 1: Outputs terminated with 50Ω to V
CC
- 2V.
TABLE 4B. AC CHARACTERISTICS, V
CC
= 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 215 MHz
t
PD
Propagation Delay; NOTE 1
ƒ 215MHz
0.8 2 ns
tsk(pp) Part-to-Part Skew; NOTE 2, 3 250 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% @ 50MHz 300 700 ps
odc Output Duty Cycle 40 60 %
All parameters measured at 133MHz unless noted otherwise.
NOTE 1: Measured from V
CC
/2 of the input to the differential output crossing point.
NOTE 2: Defi ned as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defi ned in accordance with JEDEC Standard 65..
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
CC
Positive Supply Voltage 2.375 2.5 2.625 V
I
EE
Power Supply Current 25 mA
85322 Data Sheet
©2016 Integrated Device Technology, Inc Revision D January 20, 20165
PARAMETER MEASUREMENT INFORMATION
PART-TO-PART SKEW
2.5V OUTPUT LOAD AC TEST CIRCUIT
3.3V OUTPUT LOAD AC TEST CIRCUIT
PROPAGATION DELAY
OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
85322 Data Sheet
©2016 Integrated Device Technology, Inc Revision D January 20, 20166
APPLICATION INFORMATION
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
V
CC
- 2V
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 1A and 1B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
TERMINATION FOR LVPECL OUTPUTS
FIGURE 1B. LVPECL OUTPUT TERMINATIONFIGURE 1A. LVPECL OUTPUT TERMINATION

85322AMLF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer Dual LVTTL/LVCMOS to LVPECL Translator
Lifecycle:
New from this manufacturer.
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