NCP1080DEG Datasheet NCP1080DER2G, NCP1080DEG | P10-P12

NCP1080

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DESCRIPTION OF OPERATION

Powered Device Interface

The PD interface portion of the NCP1080 supports the

IEEE802.3af defined operating modes: detection signature,

current source classification, inrush and operating current

limits. In order to give more flexibility to the user and also

to keep control of the power dissipation in the NCP1080,

both current limits are configurable. The device enters

operation once its programmable Vuvlo_on threshold is

reached, and operation ceases when the supplied voltage

falls below the Vuvlo_off threshold. Sufficient hysteresis

and Uvlo filter time are provided to avoid false power on/off

cycles due to transient voltage drops on the cable.

Detection

During the detection phase, the incremental equivalent

resistance seen by the PSE through the cable must be in the

IEEE802.3af standard specification range (23.75 kW to

26.25 kW) for a PSE voltage from 2.7 V to 10.1 V. In order

to compensate for the non−linear effect of the diode bridge

and satisfy the specification at low PSE voltage, the

NCP1080 presents a suitable impedance in parallel with the

25.5 kW R

det

external resistor connected between VPORTP

and VPORTN. For some types of diodes (especially

Schottky diodes), it may be necessary to adjust this external

resistor.

When the Detection_Off level is detected (typically

11.5 V) on VPORTP, the NCP1080 turns on its internal

3.3 V regulator and biasing circuitry in anticipation of the

classification phase as the next step.

Classification

Once the PSE device has detected the PD device, the

classification process begins. In classification, the PD

regulates a constant current source that is set by the external

resistor RCLASS value on the CLASS pin. Figure 6 shows

the schematic overview of the classification block. The

current source is defined as:

class

, (where V

is 1.2 V)

CLASS

VDDA1

1.2 V

VPORTP

VPORTN1,2

NCP1080

Rclass

Figure 6. Classification Block Diagram

Power Mode

When the classification hand−shake is completed, the

PSE and PD devices move into the operating mode.

Under Voltage Lock Out (UVLO)

The NCP1080 incorporates an under voltage lock out

(UVLO) circuit which monitors the input voltage and

determines when to apply power to the DC−DC controller.

To use the default settings for UVLO (see Table 3), the pin

UVLO must be connected to VPORTN

1,2

. In this case the

signature resistor has to be placed directly between

VPORTP and VPORTN

1,2

, as shown in Figure 7.

Figure 7. Default UVLO Settings

UVLO

VPORTP

VPORTN1,2

NCP1080

VPORT

Rdet

To define the UVLO threshold externally, the UVLO pin

must be connected to the center of an external resistor

divider between VPORTP and VPORTN

1,2

as shown in

Figure 8. The series resistance value of the external resistors

must add to 25.5 kW and replaces the internal signature

resistor.

Figure 8. External UVLO Configuration

UVLO

VPORTN1,2

NCP1080

VPORT

VPORTP

For a Vuvlo_on desired turn−on voltage threshold, R1 and

R2 can be calculated using the following equations:

R1 ) R2 + R

det

R2 +

1.2

ulvo_on

det

NCP1080

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When using the external resistor divider, the NCP1080 has an external reference voltage hysteresis of 15% typical.

Inrush and Operational Current Limitations

The inrush current limit and the operational current limit are programmed individually by an external Rinrush and Rilim1

resistors respectively connected between INRUSH and VPORTN

1,2

, and between ILIM1 and VPORTN

1,2

as shown in

Figure 9.

ILIM1 /

INRUSH

VDDA1

Vbg1

VDDA1

VPORTNx

Ilim_ref

NCP1080

Figure 9. Current Limitation Configuration (Inrush & Ilim1 Pins)

Ilim1

Vds_pgood

threshold

VPORTNx

Pass Switch

Inrush

I_pass_switch

NCP1080

RTN

VDS_PGOOD

VDDA1

1 V / 9.2 V

2 V

Current_limit_ON

detector

Figure 10. Inrush and Ilim1 Selection Mechanism

VDDA1

When VPORT reaches the UVLO_on level, the Cpd

capacitor is charged with the INRUSH current (in order to

limit the internal power dissipation of the pass−switch).

Once the Cpd capacitor is fully charged, the current limit

switches from the inrush current to the current limit level

(ilim1) as shown in Figure 10. This transition occurs when

both following conditions are satisfied:

1. The VDS of the pass−switch is below the

Vds_pgood low level (1 V typical).

2. The pass−switch is no longer in current limit

mode, meaning the gate of the pass−switch is

“high” (above 2 V typical).

The operational current limit will stay selected as long as

Vds_pgood is true (meaning that RTN−VPORTN

1,2

below the high level of Vds_pgood). This mechanism allows

a current level transition without any current spike in the

pass−switch because the operational current limit (ilim1) is

enabled once the pass−switch is not limiting the current

anymore, meaning that the Cpd capacitor is fully charged.

Thermal Shutdown

The NCP1080 includes thermal protection which shuts

down the device in case of high power dissipation. Once the

thermal shutdown (TSD) threshold is exceeded, following

blocks are turned off:

• DC−DC controller

• Pass−switch

• VDDH and VDDL regulators

• CLASS regulator

When the TSD error disappears and if the input line

voltage is still above the UVLO level, the NCP1080

automatically restarts with the current limit set in the inrush

state, the DC−DC controller is disabled and the Css

NCP1080

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(soft−start capacitor) discharged. The DC−DC controller

becomes operational as soon as RTN−VPORTN

1,2

is below

the Vds_pgood threshold.

DC−DC Converter Controller

The NCP1080 implements a current mode DC−DC

converter controller which is illustrated in Figure 11.

VDDL

360 mV

Oscillator

COMP

Gate

Driver

PWM comp

OSC

VDDL

Blanking

time

Current Slope

Compensation

Soft−start

1.45 V

1.2 V

Current limit

comp

9 V LDO

3.3 V LDO

GATE

VDDH

ARTN

VPORTP

Set

CLK

Reset

CLK

Figure 11. DC−DC Controller Block Diagram

5 kW

10 mA

11 kW

5 mA

Internal VDDH and VDDL Regulators and Gate Driver

An internal linear regulator steps down the VPORTP

voltage to a 9 V output on the VDDH pin. VDDH supplies

the internal gate driver circuit which drives the GATE pin

and the gate of the external power MOSFET. The NCP1080

gate driver supports an external MOSFET with high Vth and

high input gate capacitance. A second LDO regulator steps

down the VDDH voltage to a 3.3 V output on VDDL. VDDL

powers the analog circuitry of the DC−DC controller.

In order to prevent uncontrolled operations, both regulators

include power−on−reset (POR) detectors which prevent the

DC−DC controller from operating when either VDDH or

VDDL is too low. In addition, an over−voltage lockout

(OVLO) on the VDDH supply disables the gate driver in case

of an open−loop converter with a configuration using the bias

winding of the transformer (see Figure 4).

Both VDDH and VDDL regulators turn on as soon as

VPORT reaches the Vuvlo_on threshold.

Error Amplifier

In non−isolated converter topologies, the high gain

internal error amplifier of the NCP1080 and the internal

1.2 V reference voltage regulate the DC−DC output voltage.

In this configuration, the feedback loop compensation

network should be inserted between the FB and COMP pins

as shown in Figures 3, 4 and 5.

In isolated topologies the error amplifier is not used

because it is already implemented externally with the shunt

regulator on the secondary side of the DC−DC controller

(see Figure 2). Therefore the FB pin must be strapped to

ARTN and the output transistor of the opto−coupler has to

be connected on the COMP pin where an internal 5 kW

pull−up resistor is tied to the VDDL supply (see Figure 11).

Soft−Start

The soft−start function provided by the NCP1080 allows

the output voltage to ramp up in a controlled fashion,

eliminating output voltage overshoot. This function is

programmed by connecting a capacitor C

between the SS

and ARTN pins.

While the DC−DC controller is in POR, the capacitor C

is fully discharged. After coming out of POR, an internal

current source of 5 mA typically starts charging the capacitor

to initiate soft−start. When the voltage on SS pin has

reached 0.45 V (typical), the gate driver is enabled and

DC−DC operation starts with a duty cycle limit which

increases with the SS pin voltage. The soft−start function is

finished when the SS pin voltage goes above 1.6 V for which

the duty cycle limit reaches its maximum value of 80%.

Soft−start can be programmed by using the following

equation:

(ms) + 0.23 C

(nF)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15

NCP1080DEG

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