NCP1080DEG Datasheet NCP1080DER2G, NCP1080DEG | P7-P9

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Recommended Operating Conditions

Operating conditions define the limits for functional operation and parametric characteristics of the device. Note that the

functionality of the device outside the operating conditions described in this section is not warranted. Operating outside the

recommended operating conditions for extended periods of time may affect device reliability.

All values concerning the DC−DC controller, VDDH and VDDL blocks are with respect to ARTN. All others are with respect

to VPORTN

1,2

(unless otherwise noted).

Table 3. OPERATING CONDITIONS

Symbol Parameter Min. Typ. Max. Units Conditions

INPUT SUPPLY

VPORT

Input supply voltage 0 57 V VPORT = VPORTP −

VPORTN

1,2

SIGNATURE DETECTION

Vsignature

Input supply voltage signature detection range 1.4 9.5 V

Rsignature Signature resistance (Note 4) 23.75 26.25

Offset_current I_VportP + I_Rtn − 1.8 5

VPORTP = RTN = 1.4 V

Sleep_current I_VportP + I_Rtn − 15 25

VPORTP = RTN = 9.5 V

CLASSIFICATION

Vcl

Input supply voltage classification range 13 20.5 V

Iclass0

Class 0: Rclass 10 kW (Note 5)

0 − 4 mA Iclass0 = I_VportP + I_Rdet

Iclass1

Class 1: Rclass 130 W (Note 5)

9 − 12 mA Iclass1 = I_VportP + I_Rdet

Iclass2

Class 2: Rclass 69.8 W (Note 5)

17 − 20 mA Iclass2 = I_VportP + I_Rdet

Iclass3

Class 3: Rclass 44.2 W (Note 5)

26 − 30 mA Iclass3 = I_VportP + I_Rdet

Iclass4

Class 4: Rclass 30.9 W (Note 5)

36 − 44 mA Iclass4 = I_VportP + I_Rdet

IDC

class

Internal current consumption during

classification (Note 6)

− 600 −

For information only

UVLO

Vuvlo_on

Default turn on voltage (VportP rising) 38 40 V UVLO pin tied to

VPORTN

1,2

Vuvlo_off Default turn off voltage (VportP falling) 29.5 32 − V UVLO pin tied to

VPORTN

1,2

Vhyst_int UVLO internal hysteresis − 6 − V UVLO pin tied to

VPORTN

1,2

Vuvlo_pr UVLO external programming range 25 − 50 V UVLO pin connected to the

resistor divider (R1 & R2).

For information only

Vhyst_ext UVLO external hysteresis − 15 − % UVLO pin connected to the

resistor divider (R1 & R2)

Uvlo_Filter UVLO on/off filter time − 90 −

4. Test done according to the IEEE802.3af 2 Point Measurement. The minimum probe voltages measured at the PoE−PD are 1.4 V and 2.4 V,

and the maximum probe voltages are 8.5 V and 9.5 V.

5. Measured with an external Rdet of 25.5 kW between VPORTP and VPORTN

1,2

, and for 13 V < VPORT < 20.5 V (with VPORT = VPORTP

– VPORTN

1,2

). Resistors are assumed to have 1% accuracy.

6. This typical current excludes the current in the Rclass and Rdet external resistors.

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Table 3. OPERATING CONDITIONS

Symbol Parameter Min. Typ. Max. Units Conditions

PASS−SWITCH AND CURRENT LIMITS

Ron

Pass−switch Rds−on − 0.6 1.2

Max Ron specified at

Tj = 130°C

I_Rinrush1

Rinrush = 150 kW (Note 7)

95 125 155 mA Measured at RTN−

VPORTN

1,2

= 3 V

I_Rinrush2

Rinrush = 57.6 kW (Note 7)

260 310 360 mA Measured at RTN−

VPORTN

1,2

= 3 V

I_Rilim1

Rilim1 = 84.5 kW (Note 7)

450 510 570 mA Current limit threshold

INRUSH AND ILIM1 CURRENT LIMIT TRANSITION

Vds_pgood

VDS required for power good status 0.8 1 1.2 V RTN−VPORTN

1,2

falling; voltage with re-

spect to VPORTN

1,2

Vds_pgood_hyst VDS hysteresis required for power good

status

− 8.2 − V Voltage with respect to

VPORTN

1,2

VDDH REGULATOR

VDDH_reg

Regulator output voltage (Notes 8 and 9)

Ivddh_load + Ivddl_load < 10 mA

with

0 < Ivddl_load < 2.25 mA

8.4 9 9.6 V

VDDH_Off Regulator turn−off voltage − VDDH_reg

+ 0.5 V

− V For information only

VDDH_lim VDDH regulator current limit

(Notes 8 and 9)

13 − 26 mA

VDDH_Por_R VDDH POR level (rising) 7.3 − 8.3 V

VDDH_Por_F VDDH POR level (falling) 6 − 7 V

VDDH_ovlo VDDH over−voltage level (rising) 16 − 18.5 V

VDDL REGULATOR

VDDL_reg

Regulator output voltage (Notes 8 and 9)

0 < Ivddl_load < 2.25 mA

with

Ivddh_load + Ivddl_load < 10 mA

3.05 3.3 3.55 V

VDDL_Por_R VDDL POR level (rising) VDDL

– 0.2

− VDDL

– 0.02

VDDL_Por_F VDDL POR level (falling) 2.5 − 2.9 V

GATE DRIVER

Gate_Tr

GATE rise time (10−90%) − − 50 ns Cload = 2 nF,

VDDHreg = 9 V

Gate_Tf GATE fall time (90−10%) − − 50 ns Cload = 2 nF,

VDDHreg = 9 V

PWM COMPARATOR

VCOMP

COMP control voltage range 1.3 − 3 V For information only

7. The current value corresponds to the PoE−PD input current (the current flowing in the external Rdet and the quiescent current of the device

are included). Resistors are assumed to have 1% accuracy.

8. Power dissipation must be considered. Load on VDDH and VDDL must be limited especially if VDDH is not powered by an auxiliary winding.

9. Ivddl_load = current flowing out of the VDDL pin.

Ivddh_load = current flowing out of the VDDH pin + current delivered to the Gate Driver (function of the frequency, VDDH voltage & MOSFET

gate capacitance).

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Table 3. OPERATING CONDITIONS

Symbol Parameter Min. Typ. Max. Units Conditions

ERROR AMPLIFIER

Vbg_fb

Reference voltage 1.15 1.2 1.25 V Voltage with respect to ARTN

Av_ol DC open loop gain − 80 − dB For information only

GBW Error amplifier GBW 1 − − MHz For information only

SOFT−START

Vss

Soft−start voltage range − 1.15 − V

Vss_r Soft−start low threshold (rising edge) 0.35 0.45 0.55 V

Iss Soft−start source current 3 5 7

CURRENT LIMIT COMPARATOR

CSth

CS threshold voltage 324 360 396 mV

Tblank Blanking time − 100 − ns For information only

OSCILLATOR

DutyC

Maximum duty cycle − 80% − Fixed internally

Frange Oscillator frequency range 100 − 500 kHz

F_acc Oscillator frequency accuracy ±25 %

CURRENT CONSUMPTION

IvportP

VPORTP internal current consumption

(Note 10)

− 2.5 3.5 mA DC−DC controller off

IvportP

VPORTP internal current consumption

(Note 11)

− 4.7 6.5 mA DC−DC controller on

THERMAL SHUTDOWN

TSD

Thermal shutdown threshold 150 − − °C Tj T

= junction temperature

Thyst Thermal hysteresis − 15 − °C Tj T

= junction temperature

THERMAL RATINGS

Ambient temperature −40 − 85 °C

Junction temperature − − 125

150

°C

Parametric values guaranteed

Max 1000 hours

10.Conditions

a. No current through the pass−switch

b. DC−DC controller inactive (SS shorted to RTN)

c. No external load on VDDH and VDDL

d. VPORTP = 57 V

11. Conditions

a. No current through the pass−switch

b. Oscillator frequency = 100 kHz

c. No external load on VDDH and VDDL

d. Aux winding not used

e. 2 nF on GATE, DC−DC controller enabled

f. VPORTP = 57 V

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15

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