MAX6917
I
2
C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
22 ______________________________________________________________________________________
Crystal-Fail Detect
The crystal-fail detect circuit looks for a loss of oscillation
from the 32.768kHz oscillator for 30 cycles (typ) or more.
Both the control register and the status register are used
in the crystal-failure detection scheme (Table 1).
The crystal-fail detect circuit sets the XTAL FAIL bit in
the status register to one for a crystal failure and to zero
for normal operation. Once the status register is read,
the XTAL FAIL bit is reset to zero, if it was previously
one. If the crystal-fail-detect circuit continues to sense
a failed crystal, then the XTAL FAIL bit is set again.
On initial power-up, the crystal-fail detect circuit is
enabled. Since it takes a while for the low-power,
32.768kHz oscillator to start, the XTAL FAIL bit in the
status register can be set to one indicating a crystal
failure. The XTAL FAIL bit should be polled a number of
times to see if it is set to zero for successive polls. If the
polling is far enough apart, a few polled results could
guarantee that a maximum of 10s had elapsed since
power-on, at which time the oscillator would be consid-
ered truly failed if the XTAL FAIL bit remains one.
On subsequent power-ups, when XTAL EN is set to
one, if XTAL FAIL is set to one, time data should be
considered suspect.
The crystal-fail-detection circuit functions in both V
CC
and V
BATT
modes when the XTAL EN bit is set in the
control register.
Manual Reset Input
A logic low on MR asserts RESET. RESET remains
asserted while MR is low, and for t
RP
after it returns
high (Figure 10). MR has an internal pullup resistor, so
it can be left open if it is not used. Internal debounce
circuitry requires a minimum low time on the MR input
of 1µs with 35ns maximum glitch immunity.
Reset Output
A µP’s reset input starts the µP in a known state. The
MAX6917’s µP supervisory circuit asserts a reset to
prevent code-execution errors during power-up, power-
down, and brownout conditions. The RESET output is
guaranteed to be active for 0V < V
CC
< V
RST
, provided
V
BATT
is greater than V
BATT
(min). If V
CC
drops below
and then exceeds the reset threshold, an internal timer
keeps RESET active for the reset timeout period t
RP
;
after this interval, RESET becomes inactive high. This
condition occurs at either power-up or after a V
CC
brownout.
The RESET output is also activated when the watchdog
interrupt function is enabled but no transition is detect-
ed on the WDI input. In this case, RESET is active for
the period t
RP
before becoming inactive again. When
RESET is active, all inputs—WDI, MR, CE_IN, SDA, and
SCL—are disabled.
The MAX6917EO30 is optimized to monitor 3.0V ±10%
power supplies. Except when MR is asserted, RESET is
not active until V
CC
falls below 2.7V (3.0V - 10%), but is
guaranteed to occur before the power supply falls
below 2.5V (3.0V - 15%).
The MAX6917EO33 is optimized to monitor 3.3V ±10%
power supplies. Except when MR is asserted, RESET is
not active until V
CC
falls below 3.0V (3.0V is just above
3.3V - 10%), but is guaranteed to occur before the
power supply falls below 2.8V (3.3V - 15%).
The MAX6917EO50 is optimized to monitor 5.0V ±10%
power supplies. Except when MR is asserted, RESET is
not active until V
CC
falls below 4.5V (5.0V - 10%), but is
guaranteed to occur before the power supply falls
below 4.1V (4.1V is just below 5.0V - 15%).
Negative-Going V
CC
Transients
The MAX6917 is relatively immune to short-duration nega-
tive transients (glitches) while issuing resets to the µP dur-
ing power-up, power-down, and brownout conditions.
Therefore, resetting the µP when V
CC
experiences only
small glitches is usually not recommended. Typically, a
V
CC
transient that goes 150mV below the reset threshold
and lasts for 90µs or less does not cause a reset pulse to
be issued. A 0.1µF capacitor mounted close to the V
CC
pin provides additional transient immunity.
