Typical Operating Characteristics
(V
CC
= 3V, V
BATT
= 3V, T
A
= +25°C, unless otherwise noted.)
AC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= V
CC(MIN)
to V
CC(MAX)
, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 2)
Note 3: I
2
C serial interface is operational for V
CC
> V
RST
.
Note 4: See the Detailed Description section (V
OUT
function).
Note 5: I
BATT
is specified with SDA = SCL = V
CC
, CE_IN = WDI = GND, V
OUT
, CE_OUT, and MR floating. I
CCS
is specified with SDA =
SCL = V
CC
, CE_IN = WDI = GND, V
OUT
, CE_OUT, and MR floating.
Note 6: I
2
C serial interface operating at 400kHz, SDA pulled high, and WDI = V
CC
or GND, V
OUT
and CE_OUT floating.
Note 7: For OUT switchover to BATT, V
CC
must fall below V
RST
and V
BATT
. For OUT switchover to V
CC
, V
CC
must be above V
RST
or
above V
BATT
.
Note 8: Guaranteed by design. Not subject to production testing.
Note 9: All values are referred to V
IH (MIN)
and V
IL(MAX)
levels.
Note 10: Minimum SCL clock frequency is limited by the MAX6917 bus timeout feature, which resets the serial bus interface if either
SDA or SCL is held low for 1s to 2s. When using the burst read or write command, all 96 bytes of RAM must be read/written
within the timeout period. See the Timeout Feature section.
Note 11: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
IH(MIN)
of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
Note 12: C
b
is the total capacitance of one bus line in pF.
Note 13: The maximum t
F
for the SDA and SCL bus lines is specified at 300ns. The maximum fall time for the SDA output stage t
F
is
specified at 250ns. This allows series-protection resistors to be connected between the SDA/SCL pins and the SDA/SCL bus
lines without exceeding the maximum specified t
F
.
Note 14: The maximum t
HD:DAT
only has to be met if the device does not stretch the LOW period (t
LOW
) of the SCL signal.
