Features summary STA8058
4/14 Doc ID 14095 Rev 4
● Two I
2
C interfaces provide multi-master and slave functions, support normal and fast
I
2
C mode (400 KHz), 7/10 bit addressing modes. One I
2
C Interface is multiplexed with
one SPI, so either 2 x SPI + 1 x I
2
C or 1 x SPI + 2 x I
2
C may be used at a time.
● Enhanced interrupt controller supports 32 interrupt vectors, independently maskable,
with interrupt vector table for faster response and 16 priority levels, software
programmable for each source. Up to 2 maskable interrupts may be mapped on FIQ.
● Wake-up unit allows exiting from powerdown modes by detection of an event on two
external pins (one is active high and other is active low) or on internal Real Time Clock
alarm.
● USB unit V1.1 compliant, software configurable endpoint setting, USB suspend/resume
support
● High level data link controller (HDLC) unit supports full duplex operating mode, NRZ,
NRZI, FM0 and MANCHESTER modes, and internal 8-bit Baud Rate Generator.
● RF front-end features:
– LOW IF (4 MHz) architecture
– Compatible with GPS L1 signal
– VGA gain internally regulated
– On chip programmable PLL
– SPI interface
