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LTM8048IY#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
LTM8048
10
8048fg
For more information www.linear.com/LTM8048
APPLICATIONS INFORMATION
For most applications, the design process is straight
forward, summarized as follows:
1. Look at Table 1a (or Table 1b, if the post linear regula
-
tor is used) and find the row that has the desired input
range and output voltage.
2. Apply the recommended C
IN
, C
OUT1
, C
OUT2
, R
ADJ1
,
R
ADJ2
and C
BYP
if required.
3. Connect BIAS as indicated, or tie to an external source
up to 15V or V
IN
, whichever is less.
While these component combinations have been tested for
proper operation, it is incumbent upon the user to verify
proper operation over the intended system’s line, load and
environmental conditions. Bear in mind that the maximum
output current may be limited by junction temperature,
the relationship between the input and output voltage
magnitude and polarity and other factors. Please refer
to the graphs in the Typical Performance Characteristics
section for guidance.
Capacitor Selection Considerations
The C
IN
, C
OUT1
and C
OUT2
capacitor values in Table 1 are
the minimum recommended values for the associated op-
erating conditions. Applying capacitor values below those
indicated in T
able 1 is not recommended, and may result
in undesirable operation. Using larger values is generally
acceptable, and can yield improved dynamic response, if
it is necessar
y. Again, it is incumbent upon the user to
verify proper operation over the intended system’s line,
load and environmental conditions.
Ceramic capacitors are small, robust and have very low
ESR. However, not all ceramic capacitors are suitable.
X5R and X7R types are stable over temperature and ap
-
plied voltage and give dependable service. Other types,
including Y5V and Z5U have very large temperature and
voltage coefficients of capacitance. In an application cir
-
cuit they may have only a small fraction of their nominal
capacitance resulting in much higher output voltage ripple
than expected.
A final precaution regarding ceramic capacitors concerns
the maximum input voltage rating of the LTM8048. A
ceramic input capacitor combined with trace or cable
inductance forms a high-Q (underdamped) tank circuit. If
the LTM8048 circuit is plugged into a live supply, the input
voltage can ring to much higher than its nominal value,
possibly exceeding the device’s rating. This situation is
easily avoided; see the Hot-Plugging Safely section.
LTM8048 Table 1a. Recommended Component Values and Configuration for Specific V
OUT1
Voltages (T
A
= 25°C)
V
IN
V
OUT1
V
BIAS
C
IN
C
OUT1
R
ADJ1
3.1V to 32V 2.5V 3.1V to 15V or Open 2.2µF, 50V, 1206 100µF, 6.3V, 1210 12.4k
3.1V to 32V 3.3V 3.1V to 15V or Open 2.2µF, 50V, 1206 100µF, 6.3V, 1210 10k
3.1V to 29V 5V 3.1V to 15V or Open 2.2µF, 50V, 1206 22µF, 16V, 1210 6.98k
3.1V to 26V 8V 3.1V to 15V or Open 2.2µF, 50V, 1206 22µF, 10V, 1206 4.53k
3.1V to 24V 12V 3.1V to 15V or Open 2.2µF, 25V, 0805 10µF, 16V, 1210 3.16k/12pF*
9V to 15V 2.5V V
IN
2.2µF, 50V, 1206 100µF, 6.3V, 1210 12.4k
9V to 15V 3.3V V
IN
2.2µF, 50V, 1206 47µF, 6.3V, 1210 10k
9V to 15V 5V V
IN
2.2µF, 50V, 1206 22µF, 16V, 1210 6.98k
9V to 15V 8V V
IN
2.2µF, 50V, 1206 22µF, 10V, 1206 4.53k
9V to 15V 12V V
IN
2.2µF, 25V, 0805 10µF, 16V, 1210 3.16k
18V to 32V 2.5V 3.1V to 15V or Open 2.2µF, 50V, 1206 100µF, 6.3V, 1210 12.4k
18V to 32V 3.3V 3.1V to 15V or Open 2.2µF, 50V, 1206 47µF, 6.3V, 1210 10k
18V to 29V 5V 3.1V to 15V or Open 2.2µF, 50V, 1206 22µF, 16V, 1210 6.98k
18V to 26V 8V 3.1V to 15V or Open 2.2µF, 50V, 1206 22µF, 10V, 1206 4.53k
18V to 24V 12V 3.1V to 15V or Open 2.2µF, 50V, 1206 10µF, 16V, 1210 3.16k/12pF*
Note:
Do not allow BIAS to exceed V
IN
, a bulk input capacitor is required.
*Connect 3.16k in parallel with 12pF from ADJ to GND.
LTM8048
11
8048fg
For more information www.linear.com/LTM8048
LTM8048 Table 1b. Recommended Component Values and Configuration for Specific V
OUT2
Voltages (T
A
= 25°C)
V
IN
V
OUT1
V
OUT2
V
BIAS
C
IN
C
OUT1
C
OUT2
R
ADJ1
R
ADJ2
3.1V to 32V 1.71V 1.2V 3.1V to 15V or Open 2.2µF, 50V, 1206 100µF, 6.3V, 1210 10µF, 6.3V, 1206 16.5k Open
3.1V to 32V 2.02V 1.5V 3.1V to 15V or Open 2.2µF, 50V, 1206 100µF, 6.3V, 1210 10µF, 6.3V, 1206 14.7k 2.32M
3.1V to 32V 2.34V 1.8V 3.1V to 15V or Open 2.2µF, 50V, 1206 100µF, 6.3V, 1210 10µF, 6.3V, 1206 13.3k 1.07M
3.1V to 32V 3.08V 2.5V 3.1V to 15V or Open 2.2µF, 50V, 1206 100µF, 6.3V, 1210 10µF, 6.3V, 1206 10.5k 487k
3.1V to 32V 3.92V 3.3V 3.1V to 15V or Open 2.2µF, 50V, 1206 47µF, 6.3V, 1210 10µF, 6.3V, 1206 8.66k 294k
3.1V to 29V 5.7V 5V 3.1V to 15V or Open 2.2µF, 50V, 1206 22µF, 16V, 1210 10µF, 6.3V, 1206 6.19k 162k
3.1V to 26V 8.85V 8V 3.1V to 15V or Open 2.2µF, 50V, 1206 22µF, 10V, 1206 10µF, 10V, 1206 4.12k 88.7k
3.1V to 21V 13V 12V 3.1V to 15V or Open 2.2µF, 25V, 0805 10µF, 16V, 1210 10µF, 16V, 1206 2.94k/12pF* 56.2k
9V to 15V 1.71V 1.2V V
IN
2.2µF, 50V, 1206 100µF, 6.3V, 1210 10µF, 6.3V, 1206 16.5k Open
9V to 15V 2.02V 1.5V V
IN
2.2µF, 50V, 1206 100µF, 6.3V, 1210 10µF, 6.3V, 1206 14.7k 2.32M
9V to 15V 2.34V 1.8V V
IN
2.2µF, 50V, 1206 100µF, 6.3V, 1210 10µF, 6.3V, 1206 13.3k 1.07M
9V to 15V 3.08V 2.5V V
IN
2.2µF, 50V, 1206 100µF, 6.3V, 1210 10µF, 6.3V, 1206 10.5k 487k
9V to 15V 3.92V 3.3V V
IN
2.2µF, 50V, 1206 47µF, 6.3V, 1210 10µF, 6.3V, 1206 8.66k 294k
9V to 15V 5.7V 5V V
IN
2.2µF, 50V, 1206 22µF, 16V, 1210 10µF, 6.3V, 1206 6.19k 162k
9V to 15V 8.85V 8V V
IN
2.2µF, 50V, 1206 22µF, 10V, 1206 10µF, 10V, 1206 4.12k 88.7k
9V to 15V 13V 12V V
IN
2.2µF, 25V, 0805 10µF, 16V, 1210 10µF, 16V, 1206 2.94k/12pF* 56.2k
18V to 32V 1.71V 1.2V 3.1V to 15V or Open 2.2µF, 50V, 1206 100µF, 6.3V, 1210 10µF, 6.3V, 1206 16.5k Open
18V to 32V 2.02V 1.5V 3.1V to 15V or Open 2.2µF, 50V, 1206 100µF, 6.3V, 1210 10µF, 6.3V, 1206 14.7k 2.32M
18V to 32V 2.34V 1.8V 3.1V to 15V or Open 2.2µF, 50V, 1206 100µF, 6.3V, 1210 10µF, 6.3V, 1206 13.3k 1.07M
18V to 32V 3.08V 2.5V 3.1V to 15V or Open 2.2µF, 50V, 1206 100µF, 6.3V, 1210 10µF, 6.3V, 1206 10.5k 487k
18V to 32V 3.92V 3.3V 3.1V to 15V or Open 2.2µF, 50V, 1206 47µF, 6.3V, 1210 10µF, 6.3V, 1206 8.66k 294k
18V to 29V 5.7V 5V 3.1V to 15V or Open 2.2µF, 50V, 1206 22µF, 16V, 1210 10µF, 6.3V, 1206 6.19k 162k
18V to 26V 8.85V 8V 3.1V to 15V or Open 2.2µF, 50V, 1206 22µF, 10V, 1206 10µF, 10V, 1206 4.12k 88.7k
Note:
Do not allow BIAS to exceed V
IN
, a bulk input capacitor is required.
*Connect 2.94k in parallel with 12pF from ADJ to GND.
APPLICATIONS INFORMATION
BIAS Pin Considerations
The BIAS pin is the output of an internal linear regulator
that powers the LTM8048’s internal circuitry. It is set to
3V and must be decoupled with a low ESR capacitor of at
least 4.7μF. The LTM8048 will run properly without apply
-
ing a voltage to this pin, but will operate more efficiently
and dissipate less power if a voltage greater than 3.1V is
applied. At low V
IN
, the LTM8048 will be able to deliver
more output current if BIAS is 3.1V or greater. Up to 32V
may be applied to this pin, but a high BIAS voltage will
cause excessive power dissipation in the internal circuitry.
For applications with an input voltage less than 15V, the
BIAS pin is typically connected directly to the V
IN
pin. For
input voltages greater than 15V, it is preferred to leave the
BIAS pin separate from the V
IN
pin, either powered from
a separate voltage source or left running from the internal
regulator. This has the added advantage of keeping the
physical size of the BIAS capacitor small. Do not allow
BIAS to rise above V
IN
.
Soft-Start
For many applications, it is necessary to minimize the
inrush current at start-up. The built-in soft-start circuit
significantly reduces the start-up current spike and output
voltage overshoot by applying a capacitor from SS to GND.
When the LTM8048 is enabled, whether from V
IN
reaching
a sufficiently high voltage or RUN being pulled high, the
LTM8048 will source approximately 10µA out of the SS
pin. As this current gradually charges the capacitor from
SS to GND, the LTM8048 will correspondingly increase
the power delivered to the output, allowing for a graceful
turn-on ramp.
LTM8048
12
8048fg
For more information www.linear.com/LTM8048
APPLICATIONS INFORMATION
Isolation and Working Voltage
The LTM8048 isolation is tested by tying all of the primary
pins together, all of the secondary pins together and
subjecting the two resultant circuits to a differential of
±725VDC for one second. This establishes the isolation
voltage rating, but it does not determine the working volt
-
age rating, which is subject to the application board layout
and possibly other factors. The metal to metal separation
of the primary and secondary throughout the LTM8048
substrate is 0.44mm.
ADJ and Line Regulation
For V
OUT
greater than 8V, a capacitor connected from ADJ
to GND improves line regulation. Figure 1 shows the ef-
fect of three capacitance values applied to ADJ for a load
of 15mA. No capacitance has poor line regulation, while
12pF has improved line regulation. As the capacitance
increases, the line regulation begins to degrade again, but
in the opposite direction as having too little capacitance.
Furthermore,
too
much capacitance from ADJ to GND may
increase the minimum load required for proper regulation.
resistor from the R
ADJ2
pin to GND; the value of R
ADJ2
can be calculated by the equation:
R
ADJ2
=
608.78
V
OUT2
– 1.22
kΩ
V
OUT1
to V
OUT
–
Reverse Voltage
The LTM8048 cannot tolerate a reverse voltage from V
OUT1
to V
OUT
–
during operation. If V
OUT
–
raises above V
OUT1
during operation, the LTM8048 may be damaged. To protect
against this condition, a low forward drop power Schottky
diode has been integrated into the LTM8048, anti-parallel
to V
OUT1
/V
OUT
–
. This can protect the output against many
reverse voltage faults. Reverse voltage faults can be both
steady state and transient. An example of a steady state
voltage reversal is accidentally misconnecting a powered
LTM8048 to a negative voltage source. An example of
transient voltage reversals is a momentary connection to
a negative voltage. It is also possible to achieve a V
OUT1
reversal if the load is short-circuited through a long cable.
The inductance of the long cable forms an LC tank circuit
with the V
OUT1
capacitance, which drive V
OUT1
negative.
Avoid these conditions.
V
OUT2
Post Regulator Bypass Capacitance and Low
Noise Performance
The V
OUT2
linear regulator may be used with the addition
of a 0.01μF bypass capacitor from V
OUT
to the BYP pin
to lower output voltage noise. A good quality low leakage
capacitor, such as a X5R or X75 ceramic, is recommended.
This capacitor will bypass the reference of the regulator,
lowering the output voltage noise to as low as 20µV
RMS
.
Using a bypass capacitor has the added benefit of improv-
ing transient response.
Safety Rated Capacitors
Some applications require safety rated capacitors, which
are high voltage capacitors that are specifically designed
and rated for AC operation and high voltage surges. These
capacitors are often certified to safety standards such as UL
60950, IEC 60950 and others. In the case of the L
TM8048,
Figure 1. For Higher Output Voltages, the LTM8048 Requires
Some Capacitance from ADJ to GND for Proper Line Regulation
V
OUT2
Post Regulator
V
OUT2
is produced by a high performance low dropout
300mA regulator. At full load, its dropout is less than
430mV over temperature. Its output is set by applying a
V
IN
(V)
V
OUT
(V)
12.50
11.75
12.25
10.75
11.25
12.00
11.50
11.00
8048 F01
0 10
25
20155
NO CAP
12pF
18pF
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

LTM8048IY#PBF

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Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 725VDC Isolated DC/DC Module Converter with LDO Post Regulator
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