LTM8048
14
8048fg
For more information www.linear.com/LTM8048
APPLICATIONS INFORMATION
bypass capacitor of the LTM8048. However, these capaci-
tors can cause problems if the LTM8048 is plugged into a
live supply
(see Linear Technology Application Note 88 for
a complete discussion). The low loss ceramic capacitor
combined with stray inductance in series with the power
source forms an underdamped tank circuit, and the volt
-
age at the V
IN
pin of the LTM8048 can ring to more than
twice the nominal input voltage, possibly exceeding the
LTM8048’s rating and damaging the part. A similar phe
-
nomenon can occur inside the LTM8048 module, at the
output of the integrated EMI filter, with the same potential
of damaging the part. If the input supply is poorly con
-
trolled or the user will be plugging the LTM8048 into an
energized supply, the input network should be designed
to prevent this overshoot. This can be accomplished by
installing a small resistor in series to V
IN
, but the most
popular method of controlling input voltage overshoot is
adding an electrolytic bulk capacitor to the V
IN
or f
IN
net.
This capacitor’s relatively high equivalent series resistance
damps the circuit and eliminates the voltage overshoot.
The extra capacitor improves low frequency ripple filter
-
ing and can slightly improve the efficiency of the circuit,
though it can be a large component in the circuit.
Thermal Considerations
The
LTM8048 output current may need to be derated if it
is required to operate in a high ambient temperature. The
amount of current derating is dependent upon the input
voltage, output power and ambient temperature. The
temperature rise curves given in the Typical Performance
Characteristics section can be used as a guide. These curves
were generated by the LTM8048 mounted to a 58cm
2
4-layer FR4 printed circuit board. Boards of other sizes
and layer count can exhibit different thermal behavior, so
it is incumbent upon the user to verify proper operation
over the intended system’s line, load and environmental
operating conditions.
For increased accuracy and fidelity to the actual application,
many designers use FEA to predict thermal performance.
To that end, the Pin Configuration section of the data sheet
typically gives four thermal coefficients:
θ
JA
: Thermal resistance from junction to ambient
θ
JCbottom
: Thermal resistance from junction to the bot-
tom of the product case
θ
JCtop
: Thermal resistance from junction to top of the
product case
θ
JCboard
: Thermal resistance from junction to the printed
circuit board.
While the meaning of each of these coefficients may seem
to be intuitive, JEDEC has defined each to avoid confu
-
sion and inconsistency. These definitions are given in
JESD 51-12, and are quoted or paraphrased as follows:
θ
JA
is the natural convection junction-to-ambient air
thermal resistance measured in a one cubic foot sealed
enclosure. This environment is sometimes referred to
as still air although natural convection causes the air to
move. This value is determined with the part mounted to a
JESD 51-9 defined test board, which does not reflect an
actual application or viable operating condition.
θ
JCbottom
is the junction-to-board thermal resistance with
all of the component power dissipation flowing through the
bottom of the package. In the typical µModule converter,
the bulk of the heat flows out the bottom of the package,
but there is always heat flow out into the ambient envi
-
ronment. As a result, this thermal resistance value may
be
useful
for comparing packages but the test conditions
don’t generally match the user’s application.
θ
JCtop
is determined with nearly all of the component power
dissipation flowing through the top of the package. As the
electrical connections of the typical µModule converter are
