REV. 0–12–
AD9860/AD9862
REGISTER MAP (0x00–0x3F)
1
Register Name Address
2
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
General 0 SDIO BiDir LSB First Soft Reset
Rx Power Down 1 V
REF
(diff) V
REF
Rx Digital Rx Channel B Rx Channel A Buffer B Buffer A All Rx
Rx A2Byp Buffer A RxPGA A
Rx B3Byp Buffer B RxPGA B
Rx Misc 4
HS Duty Cycle
Shared Ref Clk Duty
Rx I/F 5 Three State Rx Retime Twos Inv RxSync Mux Out
Complement
Rx Digital 6 2 Channel Keep –ve Hilbert Decimate
RSV 7
Reserved for Future Use
Tx Power Down 8 Alt Timing TxOff Enable Tx Digital Tx Analog Power Down [2:0]
Mode
RSV9 Reserved for Future Use
Tx A Offset 10
DAC A Offset [1:0] DAC A Offset
Direction
Tx A Offset 11 DAC A Offset [9:2]
Tx B Offset 12
DAC B Offset [1:0] DAC B Offset
Direction
Tx B Offset 13 DAC B Offset [9:2]
Tx A Gain 14
DAC A Coarse Gain DAC A Fine Gain
Tx B Gain 15 DAC B Coarse Gain DAC B Fine Gain
Tx PGA Gain 16
Tx PGA Gain
Tx Misc 17 Slave Enable Tx PGA Fast
Tx I/F 18 Tx Retime Q/I Order Inv TxSync Twos Inverse 2 Edges Interleaved
Complement Sample
Tx Digital 19 2 Data Paths Keep –ve Hilbert Interpolation Control
Tx Modulator 20 Neg. Fine Tune Fine Mode Real Mix Neg. Coarse Tune Coarse Modulation
NCO Tuning
Word
21 FTW [7:0]
NCO Tuning
Word
22 FTW [15:8]
NCO Tuning
Word
23 FTW [23:16]
DLL 24 Reserved Input Control ADC Div 2 DLL Multiplier DLL DLL
Clock Power Down FAST
CLKOUT 25 CLKOUT2 Divide Factor Inv2 Dis2 Inv1 Dis1
Aux ADC A2 26
Aux ADC A2 Data [1:0]
Aux ADC A2 27 Aux ADC A2 Data [9:2]
Aux ADC A1 28
Aux ADC A1 Data [1:0]
Aux ADC A1 29 Aux ADC A1 Data [9:2]
Aux ADC B2 30
Aux ADC B2 Data [1:0]
Aux ADC B2 31 Aux ADC B2 Data [9:2]
Aux ADC B1 32
Aux ADC B1 Data [1:0]
Aux ADC B1 33 Aux ADC B1 Data [9:2]
Aux ADC Control 34 Aux SPI SelBnot A Refsel B Select B Start B Refsel A Select A Start A
Aux ADC Clock 35 CLK/4
Aux DAC A 36
Aux DAC A
Aux DAC B 37
Aux DAC B
Aux DAC C
38
Aux DAC C
Aux DAC 39 Slave Enable Update C Update B Update A
Update Aux DAC 40 Power Down C Power Down B Power Down A
DAC Control 41 Inv C Inv B Inv A
SigDelt 42 Sigma-Delta Control Word [3:0] Flag
SigDelt 43 Sigma-Delta Control Word [11:4]
ADC Low Power 49, 50
Low Power Register for Rx Path Operation below 32 MSPS
RSV 44–62
Reserved for Future Use
63 Chip Rev ID
NOTES
1
When writing to a register with unassigned register bit(s), a logic low must be written to the unassigned bit(s). By default, after power up or RESET, all registers
are set low, except for the bits in the shaded boxes, which are set high.
2
Decimal
Purpose
SPI Setup
Receive
Path
Setup
Transmit
Path
Setup
NCO
Setup
Clock
Setup
Auxiliary
ADC Data
and Setup
Auxiliary
DAC Data
and Setup
Sigma-
Delta Data
and Setup
Rx Low
Power
Reserved
Chip ID
