6.42
IDT70V261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Industrial and Commercial Temperature Ranges
10
3040 drw 11
t
DW
t
APS
ADDR
"A"
t
WC
DATA
OUT "B"
MATCH
t
WP
R/W
"A"
DATA
IN "A"
ADDR
"B"
t
DH
VALID
(1)
MATCH
BUSY
"B"
t
BDA
VALID
t
BDD
t
DDD
(3)
t
WDD
t
BAA
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(6)
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = V
IH)".
2. To ensure that the earlier of the two ports wins.
3. t
BDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. "X" in part number indicates power rating (S or L).
Timing Waveform of write with Port-to-Port Read and BUSY
(2,4,5)
NOTES:
1. To ensure that the earlier of the two ports wins. t
APS is ignored for M/S = VIL (SLAVE).
2. CE
L = CER = VIL
3. OE = VIL for the reading port.
4. If M/S = V
IL (SLAVE), then BUSY is an input (BUSY"A" = VIH and BUSY"B" = "don't care", for this example).
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
70V261X25
Com'l
& Ind
70V261X35
Com'l Only
70V261X55
Com'l Only
Symbol Parameter Min.Max.Min.Max.Min.Max.Unit
BUSY TIMING (M/S = V
IH
)
t
BAA
BUSY Access Time from Address Match
____
25
____
35
____
45 ns
t
BDA
BUSY Disable Time fro m Addre ss Not Match
____
25
____
35
____
45 ns
t
BAC
BUSY Access Time from Chip Enable Low
____
25
____
35
____
45 ns
t
BDC
BUSY Disable Time from Chip Enable High
____
25
____
35
____
45 ns
t
APS
Arbitration Priority Set-up Time
(2 )
5
____
5
____
5
____
ns
t
BDD
BUSY Disable to Valid Data
(3 )
____
35
____
40
____
50 ns
t
WH
Write Hold After BUSY
(5 )
20
____
25
____
25
____
ns
BUSY INPUT TIMING (M/S = VIL)
t
WB
BUSY Input to Write
(4 )
0
____
0
____
0
____
ns
t
WH
Write Hold After BUSY
(5 )
20
____
25
____
25
____
ns
PORT-TO-PORT DELAY TIMING
t
WDD
Write Pulse to Data Delay
(1 )
____
55
____
65
____
85 ns
t
DD D
Write Data Valid to Read Data Delay
(1 )
____
50
____
60
____
80 ns
2945 tbl 13
