AP7312
DUAL 150mA LOW QUIESCENT CURRENT FAST
TRANSIENT LOW DROPOUT LINEAR REGULATOR
AP7312
Document number: DS35133 Rev. 2 - 2
5 of 18
www.diodes.com
January 2011
© Diodes Incorporated
NEW PRODUCT
Electrical Characteristics
(T
A
= 25
o
C, V
IN
= V
OUT
+1V, C
IN
= 1uF, C
OUT
= 1uF, V
EN
= V
IN
, unless otherwise stated)
Symbol Parameter Test Conditions Min Typ. Max Unit
V
REF
ADJ Reference Voltage
(Adjustable version)
I
OUT
= 0mA 0.8 V
I
ADJ
ADJ Leakage (Adjustable version) 0.1 1 μA
V
OUT
Output Voltage Accuracy
T
A
= -40
o
C to 85
o
C,
I
OUT
= 10% of I
OUT-Ma
-2 2 %
ΔV
OUT
/ΔV
IN
/V
Line Regulation
V
IN
= (V
OUT
+1V) to V
IN-Max
,
V
EN
= V
IN
, I
OUT
= 1mA
0.01 0.20 %/V
ΔV
OUT
/V
OUT
Load Regulation
V
IN
= (V
OUT
+1V) to V
IN-Max
,
I
OUT
= 1mA to 150mA
-0.6 0.6 %
V
Dropout
Dropout Voltage (Note 4)
V
OUT
< 2.5V, I
OUT
= 150mA 200 300
mV
V
OUT
≥ 2.5V, I
OUT
= 150mA 150 200
I
Q
Input Quiescent Current (2 channels) V
EN
= V
IN
, I
OUT
= 0mA 60 80 μA
I
SHDN
Input Shutdown Current V
EN
= 0V, I
OUT
= 0mA 0.1 1
μA
I
LEAK
Input Leakage Current V
EN
= 0V, OUT grounded 0.1 1
μA
t
ST
Start-up Time
V
EN
= 0V to 2.0V in 1μs,
I
OUT
= 150mA
150 μs
PSRR
PSRR (Note 5)
V
IN
= [V
OUT
+1V]V
DC
+ 0.5V
ppAC
,
f = 1kHz, I
OUT
= 50mA
60 65 dB
I
SHORT
Short-circuit Current
V
IN
= V
IN-Min
to V
IN-Max
,
V
OUT
= 1/4 target V
OUT
60 mA
I
LIMIT
Current limit
V
IN
= V
IN-Min
to V
IN-Max
,
V
OUT
/R
OUT
= 0.6A
200 300 mA
V
IL
EN Input Logic Low Voltage V
IN
= V
IN-Min
to V
IN-Max
0.4 V
V
IH
EN Input Logic High Voltage V
IN
= V
IN-Min
to V
IN-Max
1.4 V
I
EN
EN Input Current V
IN
= 0V or V
IN-Max
-1 1 μA
T
SHDN
Thermal shutdown threshold 165
°C
T
HYS
Thermal shutdown hysteresis 30
°C
θ
JA
Thermal Resistance Junction-to-Ambient
SOT26 (Note 6) 140
o
C/W
DFN2018-6 (Note 7) 60
Notes: 4. Dropout voltage is the voltage difference between the input and the output at which the output voltage drops 2% below its nominal value.
5. This specification is guaranteed by design.
6. Test condition for SOT26: Device mounted on FR-4 substrate PC board, with minimum recommended pad layout
7. Test condition for DFN2018-6: Device mounted on FR-4 2-layer board,2oz copper, with minimum recommended pad on top layer and 3 vias to
bottom layer.
