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16
DC Bias Operating Conditions
Table 6. DC BIAS OPERATING CONDITIONS
Description Symbol Minimum Nominal Maximum Units Notes
Substrate V
SUB
C,L
0 V
Reset Drain Bias (Color) V
RD
C,L
11.5 12.0 12.5 V
Output Buffer Supply V
DD
C,L
11.5 12.0 12.5 V
Output Bias Current/Channel I
VIDPIN
−4.0 −6.0 −8.0 mA 1
Light Shield/Drain Bias V
LS
11.5 12.0 12.5 V
Test Pin − Input Gate V
IG
C,L
0 V
Test Pin − Input Diode V
ID
C,L
12.0 V
1. A current sink must be supplied for each output. Load capacitance should be minimized so as not to limit bandwidth. The values of R
X
and
R
L
should be chosen to optimize for a given operating frequency, but. Rx should not be less than 75 W. The values shown in Figure 23 below
represent one possible solution.
Typical Output Bias/Buffer Circuit
Figure 23. Typical Output Bias/Buffer Circuit
To Device
Output Pin: VIDx
(Minimize Path Length)
BFR90
or Equiv.
V
DD
R
X
= 120 W
R
L
= 600 W*
Buffered Output
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AC Operating Conditions
Table 7. AC ELECTRICAL CHARACTERISTICS
Description Symbol Minimum Nominal Maximum Units Notes
CCD Element Duration 1e = 1/f
CLK
50 50 ns 1 e Count
f1L, f1C, f2L, fC2, Rise Time
t
R
30 ns Typical
Line/Integration Period 1L = t
INT
0.1064 2.128 ms 2128 e Counts
PD−CCD Transfer Period t
PD
1,000 ns 8 e Counts
Transfer Gate 1 Clear t
TG1
500 1,000 ns 1 e Count
Transfer Gate 2 Clear t
TG2
500 1,000 ns 1 e Count
Reset Pulse Duration t
RST
9 ns 1
Clamp to f2 Delay
t
CD
5 ns 2
Sample to Reset Edge Delay t
SD
5 ns 2
LOG Gate Duration t
LOG1
1,000 ns
LOG Gate Clear t
LOG2
1,000 ns
1. Minimum values given are for 20 MHz CCD operation.
2. Recommended delays for Correlated Double Sampling (CDS) of output.
Table 8. CLOCK LEVELS
Description Symbol Minimum Nominal Maximum Units
CCD Readout Clocks High
V
f
1CH
, V
f
2CH
, V
f
1LH
, V
f
2LH
4.6 5.0 V
CCD Readout Clocks Low
V
f
1CL
, V
f
2CL
, V
f
1LL
, V
f
2LL
−0.1 0.0 0.1 V
Transfer Clocks High V
TGLH
, V
TG1H
, V
TG2H
4.6 5.0 V
Transfer Clocks Low V
TGLL
, V
TG1L
, V
TG2L
−0.1 0.0 0.1 V
Reset Clock High
V
f
RCH
, V
f
RLH
4.6 5.0 V
Reset Clock Low
V
f
RCL
, V
f
RLL
−0.1 0.0 0.1 V
1. Care should be taken to insure that low rail overshoot does not exceed −0.5 VDC. Exceeding this value may result in non-photogenerated
charged being injected into the video signal.
2. Connect pin to ground potential for applications where exposure control is not required.
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18
TIMING
Requirements and Characteristics
Table 9. CLOCK LINE CAPACITANCE
Description Symbol Minimum Nominal Maximum Units Notes
CHROMA
Phase 1 Clock Capacitance
C
f
1C
758 pF 1
Phase 2 Clock Capacitance
C
f
2C
558 pF 1
Transfer Gate 1 Capacitance C
TG1C
440 pF
Transfer Gate 2 Capacitance C
TG2C
222 pF
Reset Gate Capacitance
C
f
RC
6 pF
LUMA
Phase 1 Clock Capacitance
C
f
1L
397 pF 1
Phase 2 Clock Capacitance
C
f
2L
302 pF 1
Transfer Gate Capacitance C
TGL
92 pF
Reset Gate Capacitance
C
f
RL
6 pF
1. This is the total load capacitance per CCD phase. Since the CCDs are driven from both ends of the sensor, the effective load capacitance
per drive pin is approximately half the value listed.
Figure 24. Timing Diagram
Line Timing − Full Resolution Mode
1 Pixel
First Dark Reference Pixel Data Valid
(5th H2 Falling Edge)
4 Blank
Pixels*
12 Dark
Pixels*
2098 Active Pixels*
12 Dark
Pixels*
2 Blank
Pixels*
4 Blank
Pixels*
T
ransfer Timing − Full Resolution Mode
f1C, f1L
f2C, f2L,
f2SC
TG1C, TGL
TG2C
t
INT
f1C, f1L
f2C, f2L,
f2SC
TG1C, TGL
TG2C
t
PD
t
TG1
t
TG2
* Pixel counts are per output.

KLI-2104-DAA-EB-AA

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Image Sensors LINEAR CCD IMAGE SENSOR
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New from this manufacturer.
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