KLI−2104
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18
TIMING
Requirements and Characteristics
Table 9. CLOCK LINE CAPACITANCE
Description Symbol Minimum Nominal Maximum Units Notes
CHROMA
Phase 1 Clock Capacitance
C
f
1C
− 758 − pF 1
Phase 2 Clock Capacitance
C
f
2C
− 558 − pF 1
Transfer Gate 1 Capacitance C
TG1C
− 440 − pF
Transfer Gate 2 Capacitance C
TG2C
− 222 − pF
Reset Gate Capacitance
C
f
RC
− 6 − pF
LUMA
Phase 1 Clock Capacitance
C
f
1L
− 397 − pF 1
Phase 2 Clock Capacitance
C
f
2L
− 302 − pF 1
Transfer Gate Capacitance C
TGL
− 92 − pF
Reset Gate Capacitance
C
f
RL
− 6 − pF
1. This is the total load capacitance per CCD phase. Since the CCDs are driven from both ends of the sensor, the effective load capacitance
per drive pin is approximately half the value listed.
Figure 24. Timing Diagram
Line Timing − Full Resolution Mode
1 Pixel
First Dark Reference Pixel Data Valid
(5th H2 Falling Edge)
4 Blank
Pixels*
12 Dark
Pixels*
2098 Active Pixels*
12 Dark
Pixels*
2 Blank
Pixels*
4 Blank
Pixels*
ransfer Timing − Full Resolution Mode
f1C, f1L
f2C, f2L,
f2SC
TG1C, TGL
TG2C
t
INT
f1C, f1L
f2C, f2L,
f2SC
TG1C, TGL
TG2C
t
PD
t
TG1
t
TG2
* Pixel counts are per output.