CY7C1021CV33-15VC

CY7C1021CV33
Document #: 38-05132 Rev. *C Page 4 of 12
AC Test Loads and Waveforms
[4]
Note:
4. AC characteristics (except High-Z) for all 8-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thevenin
load shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d).
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
3.3V
OUTPUT
30 pF
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
(b)
R 317
R2
351
Rise Time: 1 V/ns
Fall Time: 1 V/ns
30 pF*
OUTPUT
Z = 50
50
1.5V
(c)
(a)
3.3V
OUTPUT
5 pF
(d)
R 317
R2
351
8-ns devices:
10-, 12-, 15-ns devices:
High-Z characteristics:
CY7C1021CV33
Document #: 38-05132 Rev. *C Page 5 of 12
Switching Characteristics
Over the Operating Range
[5]
Parameter Description
1021CV33-8 1021CV33-10
1021CV33-12 1021CV33-15
UnitMin. Max. Min. Max. Min. Max. Min. Max.
Read Cycle
t
RC
Read Cycle Time 8 10 12 15 ns
t
AA
Address to Data Valid 8 10 12 15 ns
t
OHA
Data Hold from Address Change 3 3 3 3 ns
t
ACE
CE LOW to Data Valid 8 10 12 15 ns
t
DOE
OE LOW to Data Valid 5 5 6 7 ns
t
LZOE
OE LOW to Low-Z
[6]
000 0 ns
t
HZOE
OE HIGH to High-Z
[6, 7]
456 7 ns
t
LZCE
CE LOW to Low-Z
[6]
333 3 ns
t
HZCE
CE HIGH to High-Z
[6, 7]
456 7 ns
t
PU
[8]
CE LOW to Power-Up 0 0 0 0 ns
t
PD
[8]
CE HIGH to Power-Down 8 10 12 15 ns
t
DBE
Byte Enable to Data Valid 5 5 6 7 ns
t
LZBE
Byte Enable to Low-Z 0 0 0 0 ns
t
HZBE
Byte Disable to High-Z 4 5 6 7 ns
Write Cycle
[9]
t
WC
Write Cycle Time 8 10 12 15 ns
t
SCE
CE LOW to Write End 7 8 9 10 ns
t
AW
Address Set-Up to Write End 7 8 9 10 ns
t
HA
Address Hold from Write End 0 0 0 0 ns
t
SA
Address Set-Up to Write Start 0 0 0 0 ns
t
PWE
WE Pulse Width 6 7 8 10 ns
t
SD
Data Set-Up to Write End 5 5 6 8 ns
t
HD
Data Hold from Write End 0 0 0 0 ns
t
LZWE
WE HIGH to Low-Z
[6]
333 3 ns
t
HZWE
WE LOW to High-Z
[6, 7]
456 7 ns
t
BW
Byte Enable to End of Write 6 7 8 9 ns
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7. t
HZOE
, t
HZBE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8. This parameter is guaranteed by design and is not tested.
9. The internal Write time of the memory is defined by the overlap of CE
LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Write,
and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
CY7C1021CV33
Document #: 38-05132 Rev. *C Page 6 of 12
Switching Waveforms
Notes:
10. Device is continuously selected. OE
, CE, BHE and/or BHE = V
IL
.
11. WE
is HIGH for Read cycle.
12. Address valid prior to or coincident with CE transition LOW.
Read Cycle No. 1
PREVIOUS DATA VALID DATA VALID
t
RC
t
AA
t
OHA
ADDRESS
DATA OUT
[10, 11]
Read Cycle No. 2
(OE
Controlled)
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZBE
t
PD
HIGH
OE
CE
ICC
ISB
IMPEDANCE
ADDRESS
DATA OUT
V
CC
SUPPLY
t
DBE
t
LZBE
t
HZCE
BHE, BLE
[11, 12]
CURRENT
I
CC
I
SB

CY7C1021CV33-15VC

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
IC SRAM 1M PARALLEL 44SOJ
Lifecycle:
New from this manufacturer.
Delivery:
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