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9ERS3125BKLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
IDT
TM
/ICS
TM
Embedded 56-Pin Industrial Temperature Range CK505 Compatible Clock 1612—08/19/09
ICS9ERS3125
Embedded 56-Pin Industrial Temperature Range CK505 Compatible Clock
13
Datasheet
CPU SRC DOT96 BMC133
100 100 100 100
ppm
50 125 250 125
ps
-0.50% -0.50% 0 -0.50% %
Differential Clock Tolerances
PPM tolerance
C
y
cle to C
y
cle Jitter
S
p
read
Clock Periods - Differential Outputs with Spread Spectrum Disabled
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
-c2c jitter
AbsPer
Min
-SSC
Short-Term
Average
Min
- ppm
Long-Term
Average
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Max
+SSC
Short-Term
Average
Max
+c2c jitter
100.00 9.94900 9.99900 10.00000 10.00100 10.05100 ns 1,2
133.33 7.44925 7.49925 7.50000 7.50075 7.55075 ns 1,2
166.67 5.94940 5.99940 6.00000 6.00060 6.05060 ns 1,2
200.00 4.94950 4.99950 5.00000 5.00050 5.05050 ns 1,2
266.67 3.69962 3.74962 3.75000 3.75037 3.80037 ns 1,2
333.33 2.94970 2.99970 3.00000 3.00030 3.05030 ns 1,2
400.00 2.44975 2.49975 2.50000 2.50025 2.55025 ns 1,2
SRC 100.00 9.87400 9.99900 10.00000 10.00100 10.12600 ns 1,2
DOT96 96.00 10.16563 10.41563 10.41667 10.41771 10.66771 ns 1,2
Notes
CPU
Measurement Window
UnitsSSC OFF
Center
Freq.
MHz
Clock Periods - Differential Outputs with Spread Spectrum Enabled
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
-c2c jitter
AbsPer
Min
-SSC
Short-Term
Average
Min
- ppm
Long-Term
Average
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Max
+SSC
Short-Term
Average
Max
+c2c jitter
99.75 9.94906 9.99906 10.02406 10.02506 10.02607 10.05107 10.10107 ns 1,2
133.00 7.44930 7.49930 7.51805 7.51880 7.51955 7.53830 7.58830 ns 1,2
166.25 5.94944 5.99944 6.01444 6.01504 6.01564 6.03064 6.08064 ns 1,2
199.50 4.94953 4.99953 5.01203 5.01253 5.01303 5.02553 5.07553 ns 1,2
266.00 3.69965 3.74965 3.75902 3.75940 3.75977 3.76915 3.81915 ns 1,2
332.50 2.94972 2.99972 3.00722 3.00752 3.00782 3.01532 3.06532 ns 1,2
399.00 2.44977 2.49977 2.50602 2.50627 2.50652 2.51277 2.56277 ns 1,2
SRC 99.75 9.87406 9.99906 10.02406 10.02506 10.02607 10.05107 10.17607 ns 1,2
1
Guaranteed by desi
g
n and characterization, not 100% tested in production.
CPU
2
All Lon
g
Term Accuracy specifications are
g
uaranteed with the assumption that the crystal input is tuned to exactly 14.31818MHz.
Measurement Window
UnitsSSC ON
Center
Freq.
MHz
Notes
IDT
TM
/ICS
TM
Embedded 56-Pin Industrial Temperature Range CK505 Compatible Clock 1612—08/19/09
ICS9ERS3125
Embedded 56-Pin Industrial Temperature Range CK505 Compatible Clock
14
Datasheet
General SMBus serial interface information for the ICS9ERS3125
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2
(H)
• ICS clock will
acknowledge
• Controller (host) sends the beginning byte location = N
• ICS clock will
acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will
acknowledge
• Controller (host) starts sending
Byte N through
Byte N + X -1
• ICS clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D2
(H)
• ICS clock will
acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will
acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3
(H)
• ICS clock will
acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends
Byte N + X -1
• ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
ICS (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
P
stoP bit
X Byte
Index Block Write Operation
Slave Address D2
(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T starT bit
WR WRite
RT Repeat starT
RD ReaD
Beginning Byte N
Byte N + X - 1
N Not acknowledge
PstoP bit
Slave Address D3
(H)
Index Block Read Operation
Slave Address D2
(H)
Beginning Byte = N
ACK
ACK
Data Byte Count = X
ACK
ICS (Slave/Receiver)
Controller (Host)
X Byte
ACK
ACK
IDT
TM
/ICS
TM
Embedded 56-Pin Industrial Temperature Range CK505 Compatible Clock 1612—08/19/09
ICS9ERS3125
Embedded 56-Pin Industrial Temperature Range CK505 Compatible Clock
15
Datasheet
Byte 0 FS Readback & PLL Selection Register
Bit Name Description Type 0 1 Default
7 FSLC CPU Freq. Sel. Bit (Most Significant) R Latch
6 FSLB CPU Freq. Sel. Bit R Latch
5 FSLA CPU Freq. Sel. Bit (Least Significant) R Latch
4 iAMT_EN Set via SMBus or dynamically by CK505 if detects dynamic M1 R Legacy Mode iAMT Enabled
iAMT power
on status
3 1
2 SRC_Main_SEL Select source for SRC Main RW SRC Main = PLL5 SRC Main = PLL2 0
1 SATA_SEL Select source for SATA clock RW SATA = SRC_Main SATA = PLL3 0
0 PD_Restore
1 = on Power Down de-assert return to last known state
0 = clear all SMBus configurations as if cold power-on and go to
latches open state
This bit is ignored and treated at '1' if device is in iAMT mode.
RW
Configuration Not
Saved
Configuration Saved 1
Byte 1 DOT96 Select & PLL3 Quick Config Register,
Note 1 : When 27_Select pin = 0, B1b7 Default = 1; When 27_Select pin = 1, Default = 0
Bit Name Description Type 0 1 Default
7 SRC0_SEL Select SRC0 or DOT96 RW SRC0 DOT96 Note 1
6 PLL5_SSC_SEL Select 0.5% down or center SSC RW Down spread Center spread 0
5 PLL2_SSC SEL Select 0.5% center or down SSC RW Down Center 0
4 PLL1_CF3 PLL1 Quick Confi
g
Bit 3 RW 0
3 PLL1_CF2 PLL1 Quick Config Bit 2 RW 0
2 PLL1_CF1 PLL1 Quick Config Bit 1 RW 1
1 PLL1_CF0 PLL1 Quick Config Bit 0 RW 0
0 PCI_SEL PCI_SEL RW PCI from PLL5 PCI from SRC_MAIN 1
Byte 2 Single Ended Output Enable Register
Bit Name Description Type 0 1 Default
7 REF_OE Output enable for USB RW Output Disabled Output Enabled 1
6 USB_OE Output enable for USB RW Output Disabled Output Enabled 1
5 PCIF5_OE Output enable for PCI5 RW Output Disabled Output Enabled 1
4 PCI4_OE Output enable for PCI4 RW Output Disabled Output Enabled 1
3 PCI3_OE Output enable for PCI3 RW Output Disabled Output Enabled 1
2 PCI2_OE Output enable for PCI2 RW Output Disabled Output Enabled 1
1 PCI1_OE Output enable for PCI1 RW Output Disabled Output Enabled 1
0 PCI0_OE Output enable for PCI0 RW Output Disabled Output Enabled 1
Byte 3 SRC Output Enable Register
Bit Name Description Type 0 1 Default
7 SRC11_OE Output enable for SRC11 RW Output Disabled Output Enabled 1
6 1
5 1
4 SRC8/ITP_OE Output enable for SRC8 or ITP RW Output Disabled Output Enabled 1
3 SRC7_OE Output enable for SRC7 RW Output Disabled Output Enabled 1
2 SRC6_OE Output enable for SRC6 RW Output Disabled Output Enabled 1
1 1
0 SRC4_OE Output enable for SRC4 RW Output Disabled Output Enabled 1
Byte 4 SRC/CPU/DOT Output Enable & Spread Spectrum Disable Register
Bit Name Description Type 0 1 Default
7 SRC3_OE Output enable for SRC3 RW Output Disabled Output Enabled 1
6 SATA/SRC2_OE Output enable for SATA/SRC2 RW Output Disabled Output Enabled 1
5 SRC1_OE Output enable for SRC1 RW Output Disabled Output Enabled 1
4 SRC0/DOT96_OE Output enable for SRC0/DOT96 RW Output Disabled Output Enabled 1
3 CPU1_OE Output enable for CPU1 RW Output Disabled Output Enabled 1
2 CPU0_OE Output enable for CPU0 RW Output Disabled Output Enabled 1
1 PLL5_SSC_ON Enable PLL5's spread modulation RW Spread Disabled Spread Enabled 1
0 PLL2_SSC_ON Enable PLL2's spread modulation RW Spread Disabled Spread Enabled 1
Reserved
See Table 1 : CPU Frequency Select Table
See Table 2: pin 27FIX/LCDT/SRCT_LR1/SE1,
27SS/LCDC/SRCC_LR1/SE2 Configuration
Only applies if Byte 0, bit 2 = 0.
Reserved
Reserved
Reserved
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

9ERS3125BKLF

Mfr. #:
Buy 9ERS3125BKLF
Manufacturer:
Description:
Clock Synthesizer / Jitter Cleaner EMBEDDED CK505 COMPATIBLE CLOCK
Lifecycle:
New from this manufacturer.
Delivery:
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