ESD8106MUTAG

© Semiconductor Components Industries, LLC, 2013
April, 2013 Rev. P1
1 Publication Order Number:
ESD8106/D
ESD8106
Product Preview
Transient Voltage
Suppressors
Low Capacitance ESD Protection for
USB 3.0 Interface
The ESD8106 transient voltage suppressor is specifically designed
to protect USB 3.0 interfaces by integrating two Superspeed pairs, D+
and D lines into a single protection product. Ultralow capacitance
and low ESD clamping voltage make this device an ideal solution for
protecting voltage sensitive high speed data lines. The flowthrough
style package allows for easy PCB layout and matched trace lengths
necessary to maintain consistent impedance between high speed
differential lines.
Features
Low Capacitance (0.35 pF Max, I/O to GND)
Protection for the Following IEC Standards:
IEC 6100042 Level 4
UL Flammability Rating of 94 V0
These Devices are PbFree, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
USB 3.0
MAXIMUM RATINGS (T
J
= 25°C unless otherwise noted)
Rating
Symbol Value Unit
Operating Junction Temperature Range T
J
55 to +125 °C
Storage Temperature Range T
stg
55 to +150 °C
Lead Solder Temperature
Maximum (10 Seconds)
T
L
260 °C
IEC 6100042 Contact (ESD)
IEC 6100042 Air (ESD)
ESD
ESD
±15
±15
kV
kV
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
See Application Note AND8308/D for further description of
survivability specs.
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
MARKING
DIAGRAM
Device Package Shipping
ORDERING INFORMATION
UDFN14
CASE 517CQ
http://onsemi.com
ESD8106MUTAG UDFN14
(PbFree)
3000 / Tape & Reel
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
1
14
XX = Specific Device Code
M = Date Code
G = PbFree Package
XXM
G
ESD8106
http://onsemi.com
2
Pins 5, 10
Note: Common GND – Only minimum of 1 GND connection required
Figure 1. Pin Schematic
Figure 2. Pin Configuration
Note: Pins 5, 10 are connected internally as a common ground.
Pin 8 Pin 9 Pin 11 Pin 12 Pin 13 Pin 14
ESD8106
I/O
I/O
I/O
I/O
I/O
I/O
GND
Pins 1, 2, 3, 4, 6, and 7 are not internally connected but should be connected to the op-
posite pin with PCB trace in order to maintain a flow through routing scheme.
=
ESD8106
http://onsemi.com
3
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise noted)
Symbol
Parameter
I
PP
Maximum Peak Pulse Current
V
C
Clamping Voltage @ I
PP
V
RWM
Working Peak Reverse Voltage
I
R
Maximum Reverse Leakage Current @ V
RWM
V
BR
Breakdown Voltage @ I
T
I
T
Test Current
R
DYN
Dynamic Resistance
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
UniDirectional TVS
I
PP
I
PP
V
I
I
R
I
T
V
RWM
V
CL
V
BR
V
CL
R
DYN
R
DYN
ELECTRICAL CHARACTERISTICS (T
A
= 25°C unless otherwise specified)
Parameter
Symbol Conditions Min Typ Max Unit
Reverse Working
Voltage
V
RWM
I/O Pin to GND 3.3 V
Breakdown Voltage V
BR
I
T
= 1 mA, I/O Pin to GND 4.0 5.0 V
Reverse Leakage
Current
I
R
V
RWM
= 3.3 V, I/O Pin to GND 1.0
mA
Clamping Voltage
(Note 1)
V
C
IEC6100042, ±8 kV Contact See Figures 3 and 4 V
Clamping Voltage
TLP (Note 2)
See Figures 7
through 10
V
C
I
PP
= 8 A
I
PP
= 8 A
IEC 6100042 Level 2 equivalent
(±4 kV Contact, ±4 kV Air)
8.5
4.5
V
I
PP
= 16 A
I
PP
= 16 A
IEC 6100042 Level 4 equivalent
(±8 kV Contact, ±15 kV Air)
11.4
8.0
Dynamic Resistance R
DYN
I/O Pin to GND
GND to I/O Pin
0.36
0.44
W
Junction Capacitance C
J
V
R
= 0 V, f = 1 MHz between I/O Pins and GND
V
R
= 0 V, f = 1 MHz between I/O Pins
V
R
= 0 V, f = 1 MHz, T
A
= 65°C between I/O Pins and GND
0.30
0.15
0.37
0.35
0.20
0.45
pF
1. For test procedure see Figures 5 and 6 and application note AND8307/D.
2. ANSI/ESD STM5.5.1 Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z
0
= 50 W, t
p
= 100 ns, t
r
= 4 ns, averaging window; t
1
= 30 ns to t
2
= 60 ns.
0
10
20
30
40
50
60
70
80
90
20 0 20 40 60 80 100 140120
10
Figure 3. IEC6100042 +8 kV Contact
Clamping Voltage
Figure 4. IEC6100042 8 kV Contact
Clamping Voltage
TIME (ns) TIME (ns)
VOLTAGE (V)
VOLTAGE (V)
90
80
70
60
50
40
30
20
10
0
10
20 0 20 40 60 80 100 140120

ESD8106MUTAG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
TVS Diodes / ESD Suppressors LOW CAP ESD PROTECTION
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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