ESD8106MUTAG

ESD8106
http://onsemi.com
7
Figure 13. USB 3.0 Layout Diagram
Vbus
StdA_SSTX+
D
StdA_SSTX
D+
GND_DRAIN
GND
StdA_SSRX+
StdA_SSRX
USB 3.0 Type A
Connector
ESD8106
ESD8106
http://onsemi.com
8
PCB Layout Guidelines
Steps must be taken for proper placement and signal trace
routing of the ESD protection device in order to ensure the
maximum ESD survivability and signal integrity for the
application. Such steps are listed below.
Place the ESD protection device as close as possible to
the I/O connector to reduce the ESD path to ground and
improve the protection performance.
In USB 3.0 applications, the ESD protection device
should be placed between the AC coupling
capacitors and the I/O connector on the TX
differential lanes as shown in Figure 14.
Make sure to use differential design methodology and
impedance matching of all high speed signal traces.
Use curved traces when possible to avoid unwanted
reflections.
Keep the trace lengths equal between the positive
and negative lines of the differential data lanes to
avoid common mode noise generation and
impedance mismatch.
Place grounds between high speed pairs and keep as
much distance between pairs as possible to reduce
crosstalk.
Figure 14. USB 3.0 Connection Diagram
ESD8106
http://onsemi.com
9
ESD Protection Device Technology
ON Semiconductors portfolio contains three main
technologies for low capacitance ESD protection device
which are highlighted below and in Figure 15.
ESD7000 series: Zener diode based technology. This
technology has a higher breakdown voltage (VBR)
limiting it to protecting chipsets with larger geometries.
ESD8000 series: Silicon controlled rectifier (SCR) type
technology. The key advatange for this technology is a
low holding voltage (VH) which produces a deeper
snapback that results in lower voltage over high
currents as shown in the TLP results in Figure 16. This
technology provides optimized protection for chipsets
with small geometries against thermal failures resulting
in chipset damage (also known as “hard failures”).
ESD8100 series: Low voltage punch through (LVPT)
technology. The key advatange for this technology is a
very low turn-on voltage as shown in Figure 17. This
technology provides optimized protection for chipsets
with small geometries against recoverable failures due
to voltage peaks (also known as “soft failures”).
Figure 15. ON Semiconductors Low-cap ESD Technology Portfolio
Figure 16. High Current, TLP, IV Characteristic of Each Technology
0
2
4
6
8
10
0
2
4
6
8
10
12
14
16
18
20
0 2 4 6 8 101214161820
TLP Current (A)
ESD8004
ESD7004
ESD8106
Equivalent V
IEC
(kV)
V
c
(V)

ESD8106MUTAG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
TVS Diodes / ESD Suppressors LOW CAP ESD PROTECTION
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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