34 Copyright 2010 Cirrus Logic (All Rights Reserved) DS515F2
EP9312
Universal Platform SOC Processor
Ultra DMA Data Transfer
Figure 19 through Figure 28 define the timings associated with all phases of Ultra DMA bursts. The following table
contains the values for the timings for each of the Ultra DMA modes.
Note: 1. Timing parameters shall be measured at the connector of the sender or receiver to which the parameter applies.
2. The test load for t
DVS
and t
DVH
shall be a lumped capacitor load with no cable or receivers. Timing for t
DVS
and t
DVH
shall be
met for all capacitive loads from 15 to 40 pf where all signals have the same capacitive load value.
3. t
UI
, t
MLI
and t
LI
indicate sender-to-recipient or recipient-to-sender interlocks, i.e., either sender or recipient is waiting for the
other to respond with a signal before proceeding. t
UI
is an unlimited interlock that has no maximum time value. t
MLI
is a limited
time-out that has a defined minimum. t
LI
is a limited time-out that has a defined maximum.
4. t
ZIORDY
may be greater than t
ENV
since the device has a pull up on IORDYn giving it a known state when released.
5. All IDE timing is based upon HCLK = 100 MHz.
Timing reference levels = 1.5 V
Parameter Symbol
Mode 0
(in ns)
Mode 1
(in ns)
Mode 2
(in ns)
Mode 3
(in ns)
min max min max min max min max
Cycle time allowing for asymmetry and clock variations
(from DSTROBE edge to DSTROBE edge)
t
CYCRD
112 - 73 - 54 - 39 -
Two-cycle time allowing for clock variations (from rising edge to next
rising edge or from falling edge to next falling edge of DSTROBE)
t
2CYCRD
230 - 154 - 115 - 86 -
Cycle time allowing for asymmetry and clock variations
(from HSTROBE edge to HSTROBE edge)
t
CYCWR
230 - 170 - 130 - 100 -
Two-cycle time allowing for clock variations (from rising edge to next
rising edge or from falling edge to next falling edge of HSTROBE)
t
2CYCWR
460 - 340 - 260 - 200 -
Data setup time at recipient (Read)
t
DS
15-10-7-7-
Data hold time at recipient (Read)
t
DH
8-8-8-8-
Data valid setup time at sender (Write) (Note 2)
(from data valid until STROBE edge)
t
DVS
70 - 48 - 30 - 20 -
Data valid hold time at sender (Write) (Note 2)
(from STROBE edge until data may become invalid)
t
DVH
6-6-6-6-
First STROBE time (for device to first negate DSTROBE from STOP
during a data in burst)
t
FS
0 230 0 200 0 170 0 130
Limited interlock time (Note 3)
t
LI
0 150 0 150 0 150 0 100
Interlock time with minimum (Note 3)
t
MLI
20 - 20 - 20 - 20 -
Unlimited interlock time (Note 3)
t
UI
0-0-0-0-
Maximum time allowed for output drivers to release
(from asserted or negated)
t
AZ
-10-10-10-10
Minimum delay time required for output
t
ZAH
20 - 20 - 20 - 20 -
Drivers to assert or negate (from released)
t
ZAD
0-0-0-0-
Envelope time (from DMACKn to STOP and HDMARDYn during data in
burst initiation and from DMACKn to STOP during data out burst initiation)
t
ENV
20 70 20 70 20 70 20 55
Ready-to-final-STROBE time (no STROBE edges shall be sent this long
after negation of DMARDYn)
t
RFS
-75-70-60-60
Ready-to-pause time
(that recipient shall wait to pause after negating DMARDYn)
t
RP
160 - 125 - 100 - 100 -
Maximum time before releasing IORDY
t
IORDYZ
-20-20-20-20
Minimum time before driving STROBE (Note 4)
t
ZIORDY
0-0-0-0-
Setup and hold times for DMACKn (before assertion or negation)
t
ACK
20 - 20 - 20 - 20 -
Time from STROBE edge to negation of DMARQ or assertion of STOP
(when sender terminates a burst)
t
SS
50 - 50 - 50 - 50 -
