54 Copyright 2010 Cirrus Logic (All Rights Reserved) DS515F2
EP9312
Universal Platform SOC Processor
Note: 1. Controlling Dimension: Millimeter.
2. Primary Datum C and seating plane are defined by the spherical crowns of the solder balls.
3. Dimension b is measured at the maximum solder ball diameter, parallel to Primary Datum C.
4. There shall be a minimum clearance of 0.25 mm between the edge of the solder ball and the body edge.
5. Reference Document: JEDEC MO-151, BAL-2
352 Pin BGA Pinout (Bottom View)
The following table shows the 352 pin BGA pinout. (For better understanding, compare the coordinates on the x and y
axis on Figure 40, "352 PIN BGA PINOUT", on page 55 with Figure 38, "352 Pin PBGA Pin Diagram", on page 53.
• VDD_core is CVDD.
• VDD_ring is RVDD.
• All core and ring grounds are connected together and are labelled GND.
• Other special power requirements are clearly labelled (i.e. H18=ADC_VDD and H19=ADC_GND).
• NC means that the pin is not connected.
Table R. 352 Pin Diagram Dimensions
Symbol
dimension in mm dimension in inches
MIN NOM MAX MIN NOM MAX
A 2.20 2.30 2.50 0.087 0.092 0.098
A1 - 0.60 - - 0.024 -
A2 1.12 1.17 1.22 0.044 0.046 0.048
b - 0.75 - - 0.030 -
c 0.51 0.56 0.61 0.020 0.022 0.024
D 26.80 27.00 27.20 1.055 1.063 1.071
D1 - 24.13 - - 0.950 -
D2 23.80 24.00 24.20 0.937 0.945 0.953
D3 17.95 18.00 18.05 0.707 0.709 0.711
E 26.80 27.00 27.20 1.055 1.063 1.071
E1 - 24.13 - - 0.950 -
E2 23.80 24.00 24.20 0.937 0.945 0.953
E3 17.95 18.00 18.05 0.707 0.709 0.711
e - 1.27 - - 0.050 -
ddd - - 0.15 - - 0.006
q 30° TYP 30° TYP
