CY284108
......................Document #: 38-07713 Rev. *B Page 10 of 16
FS_A, FS_B,FS_C
VTT_PWRGD#
PWRGD_VRM
VDD Clock Gen
Clock State
Clock Outputs
Clock VCO
0.2-0.3 ms
Delay
State 0
State 2 State 3
Wait for
VTT_PWRGD#
Sample Sels
Off
Off
On
On
State 1
Device is not affected,
VTT_PWRGD# is ignored
Figure 6. VTT_PWRGD# Timing Diagram
VTT_PWRGD# = Low
Delay >
0.25 ms
S1
Power Off
S0
VDD_A = 2.0V
Sample
Inputs straps
S2
Normal
Operation
Wait for <1.8 ms
Enable Outputs
S3
VTT_PWRGD# = toggle
VDD_A = off
Figure 7. Clock Generator Power-up/Run State Diagram
CY284108
......................Document #: 38-07713 Rev. *B Page 11 of 16
Absolute Maximum Conditions
Parameter Description Condition Min. Max. Unit
V
DD
Core Supply Voltage –0.5 4.6 V
V
DD_A
Analog Supply Voltage –0.5 4.6 V
V
IN
Input Voltage Relative to V
SS
–0.5 V
DD
+ 0.5 VDC
T
S
Temperature, Storage Non-functional –65 150 °C
T
A
Temperature, Operating Ambient Functional 0 70 °C
T
J
Temperature, Junction Functional 150 °C
Ø
JC
Dissipation, Junction to Case Mil-STD-883E Method 1012.1 20 °C/W
Ø
JA
Dissipation, Junction to Ambient JEDEC (JESD 51) 60 °C/W
ESD
HBM
ESD Protection
(Human Body Model)
MIL-STD-883, Method 3015 2000 V
UL-94 Flammability Rating At 1/8 in. V–0
MSL Moisture Sensitivity Level 1
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter Description Condition Min. Max. Unit
All VDDs 3.3V Operating Voltage 3.3 ± 5% 3.135 3.465 V
V
ILI2C
Input Low Voltage SDATA, SCLK 1.0 V
V
IHI2C
Input High Voltage SDATA, SCLK 2.2 V
V
IL_FS
FS_[A:B] Input Low Voltage V
SS
– 0.3 0.35 V
V
IH_FS
FS_[A:B] Input High Voltage 0.7 V
DD
+ 0.5 V
V
IMFS_C
FS_C Mid Range 0.7 2.0 V
V
IH FS_C
FS_C High Range 2.0 V
DD
+ 0.3 V
V
IL
3.3V Input Low Voltage V
SS
– 0.3 0.8 V
V
IH
3.3V Input High Voltage 2.0 V
DD
+ 0.3 V
I
IL
Input Low Leakage Current Except internal pull-up resistors, 0 < V
IN
< V
DD
–5 A
I
IH
Input High Leakage Current Except internal pull-down resistors, 0 < V
IN
< V
DD
–5A
V
OL
3.3V Output Low Voltage I
OL
= 1 mA 0.4 V
V
OH
3.3V Output High Voltage I
OH
= –1 mA 2.4 V
I
OZ
High-impedance Output Current –10 10 A
C
IN
Input Pin Capacitance 3 5 pF
C
OUT
Output Pin Capacitance 3 6 pF
L
IN
Pin Inductance –7nH
V
XIH
Xin High Voltage 0.7V
DD
V
DD
V
V
XIL
Xin Low Voltage 0 0.3V
DD
V
I
DD3.3V
Dynamic Supply Current At max. load and freq. per Figure 9 –500mA
I
PD3.3V
Power-down Supply Current PD asserted, Outputs Driven 70 mA
I
PT3.3V
Power-down Supply Current PD asserted, Outputs Tri-state 12 mA
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......................Document #: 38-07713 Rev. *B Page 12 of 16
AC Electrical Specifications
Parameter Description Condition Min. Max. Unit
Crystal
T
DC
XIN Duty Cycle The device will operate reliably with input
duty cycles up to 30/70 but the REF clock
duty cycle will not be within specification
47.5 52.5 %
T
PERIOD
XIN Period When XIN is driven from an external
clock source
69.841 71.0 ns
T
R
/ T
F
XIN Rise and Fall Times Measured between 0.3V
DD
and 0.7V
DD
–10.0ns
T
CCJ
XIN Cycle to Cycle Jitter As an average over 1-s duration 500 ps
L
ACC
Long-term Accuracy Over 150 ms 300 ppm
CPU at 0.7V
T
DC
CPUT and CPUC Duty Cycle Measured at crossing point V
OX
45 55 %
T
PERIOD
100-MHz CPUT and CPUC Period Measured at crossing point V
OX
9.997001 10.00300 ns
T
PERIOD
133-MHz CPUT and CPUC Period Measured at crossing point V
OX
7.497751 7.502251 ns
T
PERIOD
166-MHz CPUT and CPUC Period Measured at crossing point V
OX
5.998201 6.001801 ns
T
PERIOD
200-MHz CPUT and CPUC Period Measured at crossing point V
OX
4.998500 5.001500 ns
T
PERIOD
266-MHz CPUT and CPUC Period Measured at crossing point V
OX
3.748875 3.751125 ns
T
PERIOD
333-MHz CPUT and CPUC Period Measured at crossing point V
OX
2.999100 3.000900 ns
T
PERIOD
400-MHz CPUT and CPUC Period Measured at crossing point V
OX
2.499250 2.500750 ns
T
SKEW
CPU0 to CPU1 Measured at crossing point V
OX
–100ps
T
CCJ
CPUT/C Cycle to Cycle Jitter Measured at crossing point V
OX
–85ps
L
ACC
Long Term Accuracy Measured using frequency counter over
0.15seconds.
300 ppm
T
R
/ T
F
CPUT and CPUC Rise and Fall Times Measured from V
OL
= 0.175 to V
OH
= 0.525V 175 1100 ps
T
RFM
Rise/Fall Matching Determined as a fraction of
2 * (T
R
– T
F
)/(T
R
+ T
F
)
–20%
T
R
Rise Time Variation 125 ps
T
F
Fall Time Variation 125 ps
V
HIGH
Voltage High Math averages Figure 9 660 850 mV
V
LOW
Voltage Low Math averages Figure 9 –150 mV
V
OX
Crossing Point Voltage at 0.7V Swing 250 550 mV
V
OVS
Maximum Overshoot Voltage V
HIGH
+ 0.3 V
V
UDS
Minimum Undershoot Voltage –0.3 V
V
RB
Ring Back Voltage See Figure 9. Measure SE 0.2 V
SRC
T
DC
SRCT and SRCC Duty Cycle Measured at crossing point V
OX
45 55 %
T
PERIOD
100-MHz SRCT and SRCC Period Measured at crossing point V
OX
9.997001 10.00300 ns
T
SKEW
Any SRCT/C to SRCT/C Clock Skew Measured at crossing point V
OX
–250ps
T
CCJ
SRCT/C Cycle to Cycle Jitter Measured at crossing point V
OX
–125ps
L
ACC
SRCT/C Long Term Accuracy Measured at crossing point V
OX
300 ppm
T
R
/ T
F
SRCT and SRCC Rise and Fall Times Measured from V
OL
= 0.175 to V
OH
= 0.525V 175 1100 ps
T
RFM
Rise/Fall Matching Determined as a fraction of
2 * (T
R
– T
F
)/(T
R
+ T
F
)
–20%
T
R
Rise TimeVariation 125 ps
T
F
Fall Time Variation 125 ps
V
HIGH
Voltage High Math averages Figure 9 660 850 mV

CY284108ZXCT

Mfr. #:
Manufacturer:
Silicon Labs
Description:
Clock Generators & Support Products Server, CK410B
Lifecycle:
New from this manufacturer.
Delivery:
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