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CY284108ZXCT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
CY284108
........................Document #: 38-07713 Rev. *B Page 4 of 16
Control Registers
Table 3. Block Read and Block Write Protocol
Block Write Protocol Block Read Protocol
Bit Description Bit Description
1Start 1Start
8:2 Slave address – 7 bits 8:2 Slave address – 7 bits
9 Write 9 Write
10 Acknowledge from slave 10 Acknowledge from slave
18:11 Command Code – 8 bits 18:11 Command Code – 8 bits
19 Acknowledge from slave 19 Acknowledge from slave
27:20 Byte Count – 8 bits
(Skip this step if I
2
C_EN bit set)
20 Repeat start
28 Acknowledge from slave 27:21 Slave address – 7 bits
36:29 Data byte 1 – 8 bits 28 Read = 1
37 Acknowledge from slave 29 Acknowledge from slave
45:38 Data byte 2 – 8 bits 37:30 Byte Count from slave – 8 bits
46 Acknowledge from slave 38 Acknowledge
.... Data Byte /Slave Acknowledges 46:39 Data byte 1 from slave – 8 bits
.... Data Byte N –8 bits 47 Acknowledge
.... Acknowledge from slave 55:48 Data byte 2 from slave – 8 bits
.... Stop 56 Acknowledge
.... Data bytes from slave / Acknowledge
.... Data Byte N from slave – 8 bits
.... NOT Acknowledge
.... Stop
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol Byte Read Protocol
Bit Description Bit Description
1Start 1Start
8:2 Slave address – 7 bits 8:2 Slave address – 7 bits
9Write 9Write
10 Acknowledge from slave 10 Acknowledge from slave
18:11 Command Code – 8 bits 18:11 Command Code – 8 bits
19 Acknowledge from slave 19 Acknowledge from slave
27:20 Data byte – 8 bits 20 Repeated start
28 Acknowledge from slave 27:21 Slave address – 7 bits
29 Stop 28 Read
29 Acknowledge from slave
37:30 Data from slave – 8 bits
38 NOT Acknowledge
39 Stop
CY284108
........................Document #: 38-07713 Rev. *B Page 5 of 16
Byte 0: Control Register 0
Bit @Pup Name Description
7 1 RESERVED RESERVED
6 1 RESERVED RESERVED
5 1 RESERVED RESERVED
4 1 SRC[T/C]4 SRC[T/C]4 Output Enable
0 = Disable (Tri-state), 1 = Enable
3 1 SRC[T/C]3 SRC[T/C]3 Output Enable
0 = Disable (Tri-state), 1 = Enable
2 1 SRC[T/C]2 SRC[T/C]2 Output Enable
0 = Disable (Tri-state), 1 = Enable
1 1 SRC[T/C]1 SRC[T/C]1 Output Enable
0 = Disable (Tri-state), 1 = Enable
0 1 SRC[T/C]0 SRC[T/C]0 Output Enable
0 = Disable (Tri-state), 1 = Enable
Byte 1: Control Register 1
Bit @Pup Name Description
7 1 REF1 REF1 Output Enable
0 = Disable, 1 = Enable
6 1 REF0 REF0 Output Enable
0 = Disable, 1 = Enable
5 1 CPU[T/C]3 CPU[T/C]3 Output Enable
0 = Disable (Tri-state), 1 = Enable
4 1 CPU[T/C]2 CPU[T/C]2 Output Enable
0 = Disable (Tri-state), 1 = Enable
3 1 RESERVED RESERVED
2 1 CPU[T/C]1 CPU[T/C]1 Output Enable
0 = Disable (Tri-state), 1 = Enable
1 1 CPU[T/C]0 CPU[T/C]0 Output Enable
0 = Disable (Tri-state), 1 = Enable
00 CPU
SRC
PCIF
PCI
PLL1 Spread Spectrum Enable
0 = Spread off, 1 = Spread on
Byte 2: Control Register 2
Bit @Pup Name Description
7 1 PCI3 PCI3 Output Enable
0 = Disable, 1 = Enable
6 1 PCI2 PCI2 Output Enable
0 = Disable, 1 = Enable
5 1 PCI1 PCI1 Output Enable
0 = Disable, 1 = Enable
4 1 PCI0 PCI0 Output Enable
0 = Disable, 1 = Enable
3 1 PCIF2 PCIF2 Output Enable
0 = Disable, 1 = Enable
2 1 PCIF1 PCIF1 Output Enable
0 = Disable, 1 = Enable
1 1 PCIF0 PCIF0 Output Enable
0 = Disable, 1 = Enable
CY284108
........................Document #: 38-07713 Rev. *B Page 6 of 16
0 1 USB48 USB_48 Output Enable
0 = Disable, 1 = Enable
Byte 3: Control Register 3
Bit @Pup Name Description
7 0 PCIF2 Allow control of PCIF2 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
6 0 PCIF1 Allow control of PCIF1 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
5 0 PCIF0 Allow control of PCIF0 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
4 0 SRC[T/C]4 Allow control of SRC[T/C]4 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
3 0 SRC[T/C]3 Allow control of SRC[T/C]3 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
2 0 SRC[T/C]2 Allow control of SRC[T/C]2 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
1 0 SRC[T/C]1 Allow control of SRC[T/C]1 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
0 0 SRC[T/C]0 Allow control of SRC[T/C]0 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Byte 4: Control Register 4
Bit @Pup Name Description
7 0 CPU[T/C]3 CPU[T/C]3 PD drive mode
0 = Driven in power down, 1 = Tri-state
6 0 CPU[T/C]2 CPU[T/C]2 PD drive mode
0 = Driven in power down, 1 = Tri-state
5 0 CPU[T/C]1 CPU[T/C]1 PD drive mode
0 = Driven in power down, 1 = Tri-state
4 0 CPU[T/C]0 CPU[T/C]0 PD drive mode
0 = Driven in power down, 1 = Tri-state
3 0 RESERVED RESERVED
2 0 RESERVED RESERVED
1 0 RESERVED RESERVED
0 0 RESERVED RESERVED
Byte 5: Control Register 5
Bit @Pup Name Description
7 0 RESERVED RESERVED
6 0 SRC[T/C][4:0] PCI_STP#
drive mode
Stoppable SRC[T/C][4:0] drive mode upon PCI_STP# assertion
0 = Driven in PCI_STOP#, 1 = Tri-state
5 0 SRC[T/C][4:0] PWRDWN
Drive mode
SRC[T/C][4:0] PWRDWN drive mode
0 = Driven in power down, 1 = Tri-state
4 0 RESERVED RESERVED, Set = 0
3 0 RESERVED RESERVED
2 0 RESERVED RESERVED
1 0 RESERVED RESERVED
Byte 2: Control Register 2 (continued)
Bit @Pup Name Description
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

CY284108ZXCT

Mfr. #:
Buy CY284108ZXCT
Manufacturer:
Silicon Labs
Description:
Clock Generators & Support Products Server, CK410B
Lifecycle:
New from this manufacturer.
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