DS2175
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SLIP CORRECTION CAPABILITY
The 2–frame buffer depth is adequate for T–carrier and CEPT applications where short term jitter
synchronization, rather than correction of significant frequency differences, is required. The DS2175
provides an ideal balance between total delay (less than 250 microse-conds at its full depth) and slip
correction capability.
BUFFER RECENTERING
Many applications require that the buffer be recentered during system power–up and/or initialization.
Forcing ALN low recenters the buffer on the occurrence of the next frame sync boundary. A slip will
occur during this recentering if the buffer depth is adjusted. If the depth is presently optimum, no
adjustment (slip) occurs.
SLIP REPORTING
SLIP is held low for 65 SYSCLK cycles when a slip occurs. SLIP is an active–low, open collector
output. FSD indicates slip direction. When low (buffer empty) a frame of data was “repeated” at SSER
during the previous slip. When high (buffer full), a frame of data was “deleted”. FSD is updated at every
slip occurrence.
BUFFER DEPTH MONITORING
SMSYNC is a system side output pulse which indicates system side multiframe boundaries. The distance
between rising edges of RMSYNC and SMSYNC indicates the current buffer depth. Impending slip
conditions may be determined by monitoring RMSYNC and SMSYNC real time. SMSYNC is held high
for 65 SYSCLK periods.
CLOCK SELECT
Receive and system side clock frequencies are independently selectable by inputs RCLKSEL and
SCLKSEL. 1.544 MHz is selected when RCLKSEL (SCLKSEL) = 0; 2.048 MHz is selected when
RCLKSEL (SCLKSEL) = 1. In 1.544 MHz (receive) to 1.544 MHz (system) applications, the F-bit
position is passed through the receive buffer and presented at SSER immediately after the rising edge of
the system side frame sync. The F–bit position is forced to 1 in 2.048 MHz to 1.544 MHz applications.
No F–bit position exists in 2.048 MHz system side applications.
PARALLEL COMPATIBILITY
The DS2175 is compatible with parallel and serial backplanes. Channel 1 data appears at SSER after a
rising edge at SFSYNC (serial applications, S/
= 1). The device utilizes a look–ahead circuit in parallel
applications (S/
= 0), and presents data 8 clocks early as shown in Figures 4 and 5. Converting SSER to
a parallel format requires an HC595 shift register.
