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87016AYILF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
DATA SHEET
Low Skew, 1-to-16 LVCMOS/LVTTL Clock
Generator
87016I
87016I Rev C 3/23/15 1 ©2015 Integrated Device Technology, Inc.
Description
The 87016I is a low skew, 1:16 LVCMOS/LVTTL Clock Generator.
The device has four banks of four outputs and each bank can be
independently selected for 1 or 2 frequency operation. Each bank
also has its own power supply pins so that the banks can operate at
the following different voltage levels: 3.3V, 2.5V, and 1.8V. The low
impedance LVCMOS/LVTTL outputs are designed to drive 50
series or parallel terminated transmission lines.
The divide select inputs, DIV_SELA:DIV_SELD, control the output
frequency of each bank. The output banks can be independently
selected for 1 or 2 operation. The bank enable inputs,
CLK_ENA:CLK_END, support enabling and disabling each bank of
outputs individually. The CLK_ENA:CLK_END circuitry has a
synchronizer to prevent runt pulses when enabling or disabling the
clock outputs. The master reset input, MR/OE
, resets the 1/2 flip
flops and also controls the active and high impedance states of all
outputs. This pin has an internal pull-up resistor and is normally used
only for test purposes or in systems which use low power modes.
The 87016I is characterized to operate with the core at 3.3V or 2.5V
and the banks at 3.3V, 2.5V, or 1.8V. Guaranteed bank, output, and
part-to-part skew characteristics make the 87016I ideal for those
clock applications demanding well-defined performance and
repeatability.
Features
• Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs)
• Selectable differential CLK1/CLK1 or LVCMOS/LVTTL clock input
• CLK1, CLK1 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• CLK0 supports the following input types: LVCMOS, LVTTL
• Maximum output frequency: 250MHz
• Independent bank control for ÷1 or ÷2 operation
• Independent output bank voltage settings for 3.3V, 2.5V, or 1.8V
operation
• Asynchronous clock enable/disable
• Output skew: 170ps (maximum)
• Bank skew: 50ps (maximum
• Part-to-Part Skew: 800ps (maximum)
• Supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
• -40°C to 85°C ambient operating temperature
• Lead-free packaging
Block Diagram Pin Assignment
87016I
48-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
MR/OE
CLK0
CLK1
CLK1
CLK_SEL
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
CLK_ENA
CLK_ENB
CLK_ENC
CLK_END
QA0:QA3
QB0:QB3
QC0:QC3
QD0:QD3
0
1
1
0
1
0
1
0
1
0
÷1
÷2
4
4
4
4
LE
LE
LE
LE
D
D
D
D
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
VDD
CLK0
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
CLK_ENA
CLK_ENB
CLK_ENC
CLK_END
MR/OE
GND
GND
QB0
V
DDOB
QB1
GND
QB2
V
DDOB
QB3
GND
QC0
V
DDOC
QC1
QD3
V
DDOD
QD2
GND
QD1
V
DDOD
QD0
GND
QC3
V
DDOC
QC2
GND
CLK1
CLK1
CLK_SEL
GND
QA0
V
DDOA
QA1
GND
QA2
V
DDOA
QA3
V
DD
48 47 46 45 44 43 42 41 40 39 38 37
Rev C 3/23/15 2 LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR
87016I DATA SHEET
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Number Name Type Description
1, 48 V
DD
Power Positive supply pins.
2 CLK0 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
3 DIV_SELA Input Pullup
Controls frequency division for Bank A outputs. See Table 3.
LVCMOS / LVTTL interface levels.
4 DIV_SELB Input Pullup
Controls frequency division for Bank B outputs. See Table 3.
LVCMOS / LVTTL interface levels.
5 DIV_SELC Input Pullup
Controls frequency division for Bank C outputs. See Table 3.
LVCMOS / LVTTL interface levels.
6 DIV_SELD Input Pullup
Controls frequency division for Bank D outputs. See Table 3.
LVCMOS / LVTTL interface levels.
7 CLK_ENA Input Pullup
Output enable for Bank A outputs. Active HIGH. If pin is LOW, outputs drive
low. LVCMOS/LVTTL interface levels. See Table 3.
8 CLK_ENB Input Pullup
Output enable for Bank A outputs. Active HIGH. If pin is LOW, outputs drive
low. LVCMOS/LVTTL interface levels. See Table 3.
9 CLK_ENC Input Pullup
Output enable for Bank A outputs. Active HIGH. If pin is LOW, outputs drive
low. LVCMOS/LVTTL interface levels. See Table 3.
10 CLK_END Input Pullup
Output enable for Bank A outputs. Active HIGH. If pin is LOW, outputs drive
low. LVCMOS/LVTTL interface levels. See Table 3.
11 MR/OE
Input Pullup
Master reset. When LOW, resets the ÷1/÷2 flip flops and sets the outputs to
high impedance. LVCMOS / LVTTL interface levels.
12, 16, 20,
24, 28, 32,
36, 40, 44
GND Power Power supply ground
13, 15, 17, 19
QD3, QD2,
QD1, QD0
Output Bank D single-ended clock outputs. LVCMOS/LVTTL interface levels.
14, 18 V
DDOD
Power Bank D output supply pins.
21, 23, 25, 27
QC3, QC2,
QC1, QC0
Output Bank C single-ended clock outputs. LVCMOS/LVTTL interface levels.
22, 26 V
DDOC
Power Bank C output supply pins.
29, 31, 33, 35
QB3, QB2,
QB1, QB0
Output Bank C single-ended clock outputs. LVCMOS/LVTTL interface levels.
30, 34 V
DDOB
Power Bank B output supply pins.
37, 39, 41, 43
QA3, QA2,
QA1, QA0
Output Bank A single-ended clock outputs. LVCMOS/LVTTL interface levels.
38, 42 V
DDOA
Power Bank B output supply pins.
45 CLK_SEL Input Pulldown
Clock select input. When HIGH, selects CLK1, CLK1
inputs.
When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels.
46 CLK1
Input Pullup Inverting differential clock input.
47 CLK1 Input Pulldown Non-inverting differential clock input.
Rev C 3/23/15 3 LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR
87016I DATA SHEET
Table 2. Pin Characteristics
NOTE 1: V
DDOx
denotes V
DDOA,
V
DDOB,
V
DDOC,
V
DDOD.
Function Tables
Table 3. Function Table
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLUP
Input Pullup Resistor 51 k
R
PULLDOWN
Input Pulldown Resistor 51 k
C
PD
Power Dissipation
Capacitance
(per output); NOTE 1
V
DD,
V
DDOx
= 3.465V 18 pF
V
DD,
V
DDOx
= 2.625V 12 pF
V
DD
= 3.465V,
V
DDOx
= 2.625V
20 pF
V
DD
= 3.465V,
V
DDOx
= 1.89V
30 pF
V
DD
= 2.625V,
V
DDOx
= 1.89V
14 pF
R
OUT
Output Impedance 5 7 12
Inputs Outputs
MR/OE
CLK_ENx DIV_SELx Bank [A:D] Qx
Frequency
0XXHi-ZN/A
1 1 0 Active fIN/2
111ActivefIN
10XLOWN/A
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

87016AYILF

Mfr. #:
Buy 87016AYILF
Manufacturer:
IDT
Description:
Clock Generators & Support Products 16 LVCMOS OUT BUFFER/DIVIDER
Lifecycle:
New from this manufacturer.
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