Rev C 3/23/15 7 LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR
87016I DATA SHEET
Table 5C. AC Characteristics, V
DD
= 3.3V ± 5%, V
DDOx
= 2.5V ± 5%, T
A
= -40°C to 85°C
All parameters measured at 250MHz unless noted otherwise.
NOTE 1A: Measured from the V
DD
/2 of the input to V
DDOX
/2 of the output.
NOTE 1B: Measured from the differential input crossing point to V
DDOX
/2 of the output.
NOTE 2: Defined as skew within a bank with equal load conditions.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDOX
/2.
NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using
the same type of input on each device, the output is measured at V
DDOX
/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
Table 5D. AC Characteristics, V
DD
= 3.3V ± 5%, V
DDOx
= 1.8V ± 5%, T
A
= -40°C to 85°C
For NOTES, please see above, Table 5C.
Parameter Symbol Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 250 MHz
tp
LH
Propagation
Delay,
Low to High
CLK0;
NOTE 1A
2.9 3.5 4.0 ns
CLK1/CLK1
;
NOTE 1B
3.0 3.5 4.0 ns
tsk(b) Bank Skew; NOTE 2, 6 Measured on the Rising Edge 50 ps
tsk(o) Output Skew; NOTE 3, 6 Measured on the Rising Edge 170 ps
tsk(pp) Part-to-Part Skew; NOTE 4, 6 800 ps
t
R
/ t
F
Output Rise/Fall Time; NOTE 5 20% to 80% 200 700 ps
odc Output Duty Cycle
ƒ < 175MHz 45 55 %
ƒ 175MHz 40 60 %
t
EN
Output Enable Time; NOTE 5 10 ns
t
DIS
Output Disable Time; NOTE 5 10 ns
Parameter Symbol Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 250 MHz
tp
LH
Propagation
Delay,
Low to High
CLK0;
NOTE 1A
3.0 3.9 4.7 ns
CLK1/CLK1
;
NOTE 1B
3.0 3.9 4.7 ns
tsk(b) Bank Skew; NOTE 2, 6 Measured on the Rising Edge 50 ps
tsk(o) Output Skew; NOTE 3, 6 Measured on the Rising Edge 170 ps
tsk(pp) Part-to-Part Skew; NOTE 4, 6 800 ps
t
R
/ t
F
Output Rise/Fall Time; NOTE 5 20% to 80% 200 700 ps
odc Output Duty Cycle
ƒ < 175MHz 45 55 %
ƒ 175MHz 40 60 %
t
EN
Output Enable Time; NOTE 5 10 ns
t
DIS
Output Disable Time; NOTE 5 10 ns
Rev C 3/23/15 8 LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR
87016I DATA SHEET
Table 5E. AC Characteristics, V
DD
= 2.5V ± 5%, V
DDOx
= 1.8V ± 5%, T
A
= -40°C to 85°C
All parameters measured at 250MHz unless noted otherwise.
NOTE 1A: Measured from the V
DD
/2 of the input to V
DDOX
/2 of the output.
NOTE 1B: Measured from the differential input crossing point to V
DDOX
/2 of the output.
NOTE 2: Defined as skew within a bank with equal load conditions.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDOX
/2.
NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using
the same type of input on each device, the output is measured at V
DDOX
/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
Parameter Symbol Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 250 MHz
tp
LH
Propagation
Delay,
Low to High
CLK0;
NOTE 1A
3.1 4.1 5.2 ns
CLK1/CLK1
;
NOTE 1B
3.0 3.9 4.7 ns
tsk(b) Bank Skew; NOTE 2, 6 Measured on the Rising Edge 70 ps
tsk(o) Output Skew; NOTE 3, 6 Measured on the Rising Edge 210 ps
tsk(pp) Part-to-Part Skew; NOTE 4, 6 800 ps
t
R
/ t
F
Output Rise/Fall Time; NOTE 5 20% to 80% 150 700 ps
odc Output Duty Cycle
ƒ < 175MHz 45 55 %
ƒ 175MHz 40 60 %
t
EN
Output Enable Time; NOTE 5 10 ns
t
DIS
Output Disable Time; NOTE 5 10 ns
Rev C 3/23/15 9 LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR
87016I DATA SHEET
Parameter Measurement Information
3.3V Core/3.3V LVCMOS Output Load Test Circuit
3.3V Core/2.5V LVCMOS Output Load Test Circuit
2.5V Core/1.8V LVCMOS Output Load Test Circuit
2.5V Core/2.5V LVCMOS Output Load Test Circuit
3.3V Core/1.8V LVCMOS Output Load Test Circuit
Differential Input Level
SCOPE
Qx
GND
V
DD,
1.65V±5%
-1.65V±5%
V
DDO
SCOPE
Qx
GND
V
DDO
V
DD
1.25V±5%
-1.25V±5%
2.05V±5%
SCOPE
Qx
GND
V
DDO
V
DD
0.9V±5%
1.6V±0.9V
-0.9V±5%
SCOPE
Qx
GND
V
DD,
1.25V±5%
-1.25V±5%
V
DDO
SCOPE
Qx
GND
V
DD
V
DDO
0.9V±5%
2.4V±0.9V
-0.9V±5%
V
DD
GND
V
CMR
Cross Points
V
PP
CLK1
CLK1

87016AYILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products 16 LVCMOS OUT BUFFER/DIVIDER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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